With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.
Signed-off-by: Ajay Kumar <ajaykumar...@samsung.com>
Acked-by: Simon Glass <s...@chromium.org>
Acked-by: Donghwa Lee <dh09....@samsung.com>
---
Changes in V2:
-- Fix commit message. Had written VPLL instead of MPLL.
Changes in V3:
-- Added changelog in commit message.
Changes in V6:
-- Moved changelog to proper position
arch/arm/cpu/armv7/exynos/clock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index ae6d7fe..abc3272 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -741,7 +741,7 @@ void exynos5_set_lcd_clk(void)
*/
cfg = readl(&clk->src_disp1_0);
cfg &= ~(0xf);
- cfg |= 0x8;
+ cfg |= 0x6;
writel(cfg, &clk->src_disp1_0);
/*
--
1.8.0
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