If a board config file defines DIU, LPC and NFC deviders,
configure them in the SCFR1 register.
Signed-off-by: Anatolij Gustschin <ag...@denx.de>
---
arch/powerpc/cpu/mpc512x/cpu_init.c | 15 +++++++++++++++
arch/powerpc/include/asm/immap_512x.h | 6 ++++++
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc512x/cpu_init.c
b/arch/powerpc/cpu/mpc512x/cpu_init.c
index 3b29ee1..0df2888 100644
--- a/arch/powerpc/cpu/mpc512x/cpu_init.c
+++ b/arch/powerpc/cpu/mpc512x/cpu_init.c
@@ -172,6 +172,21 @@ void cpu_init_f (volatile immap_t * im)
ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
out_be32(&im->clk.scfr[0], ips_div);
+#ifdef SCFR1_LPC_DIV
+ clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK,
+ SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT);
+#endif
+
+#ifdef SCFR1_NFC_DIV
+ clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK,
+ SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT);
+#endif
+
+#ifdef SCFR1_DIU_DIV
+ clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK,
+ SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT);
+#endif
+
/*
* Enable Time Base/Decrementer
*
diff --git a/arch/powerpc/include/asm/immap_512x.h
b/arch/powerpc/include/asm/immap_512x.h
index f763a54..157e6b8 100644
--- a/arch/powerpc/include/asm/immap_512x.h
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -238,6 +238,12 @@ typedef struct clk512x {
#define SCFR1_LPC_DIV_MASK 0x00003800
#define SCFR1_LPC_DIV_SHIFT 11
+#define SCFR1_NFC_DIV_MASK 0x00000700
+#define SCFR1_NFC_DIV_SHIFT 8
+
+#define SCFR1_DIU_DIV_MASK 0x000000FF
+#define SCFR1_DIU_DIV_SHIFT 0
+
/* SCFR2 System Clock Frequency Register 2 */
#define SCFR2_SYS_DIV 0xFC000000
#define SCFR2_SYS_DIV_SHIFT 26
--
1.7.5.4
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