Support the ti814x specific register definitions within
arch-am33xx.
Signed-off-by: Matt Porter <mpor...@ti.com>
---
arch/arm/cpu/armv7/am33xx/sys_info.c | 3 +++
arch/arm/include/asm/arch-am33xx/cpu.h | 11 +++++----
arch/arm/include/asm/arch-am33xx/hardware.h | 32 +++++++++++++++++++++++++++
arch/arm/include/asm/arch-am33xx/omap.h | 7 ++++++
arch/arm/include/asm/arch-am33xx/spl.h | 5 +++++
5 files changed, 54 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c
b/arch/arm/cpu/armv7/am33xx/sys_info.c
index 507b618..402127c 100644
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -98,6 +98,9 @@ int print_cpuinfo(void)
case AM335X:
cpu_s = "AM335X";
break;
+ case TI81XX:
+ cpu_s = "TI81XX";
+ break;
default:
cpu_s = "Unknown cpu type";
break;
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 16e8a80..3d3a7c8 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -42,9 +42,10 @@
#define HS_DEVICE 0x2
#define GP_DEVICE 0x3
-/* cpu-id for AM33XX family */
+/* cpu-id for AM33XX and TI81XX family */
#define AM335X 0xB944
-#define DEVICE_ID 0x44E10600
+#define TI81XX 0xB81E
+#define DEVICE_ID (CTRL_BASE + 0x0600)
/* This gives the status of the boot mode pins on the evm */
#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
@@ -52,9 +53,11 @@
/* Reset control */
#ifdef CONFIG_AM33XX
-#define PRM_RSTCTRL 0x44E00F00
-#define PRM_RSTST 0x44E00F08
+#define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
+#elif defined(CONFIG_TI814X)
+#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
#endif
+#define PRM_RSTST (PRM_RSTCTRL + 8)
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h
b/arch/arm/include/asm/arch-am33xx/hardware.h
index 41ab2c0..786c159 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -20,9 +20,14 @@
#define __AM33XX_HARDWARE_H
#include <asm/arch/omap.h>
+#include <config.h>
/* Module base addresses */
+#ifdef CONFIG_AM33XX
#define UART0_BASE 0x44E09000
+#elif defined(CONFIG_TI814X)
+#define UART0_BASE 0x48020000
+#endif
/* DM Timer base addresses */
#define DM_TIMER0_BASE 0x4802C000
@@ -37,20 +42,39 @@
/* GPIO Base address */
#define GPIO0_BASE 0x48032000
#define GPIO1_BASE 0x4804C000
+#ifdef CONFIG_AM33XX
#define GPIO2_BASE 0x481AC000
+#endif
/* BCH Error Location Module */
#define ELM_BASE 0x48080000
/* Watchdog Timer */
+#ifdef CONFIG_AM33XX
#define WDT_BASE 0x44E35000
+#elif defined(CONFIG_TI814X)
+#define WDT_BASE 0x481C7000
+#endif
/* Control Module Base Address */
+#ifdef CONFIG_AM33XX
#define CTRL_BASE 0x44E10000
#define CTRL_DEVICE_BASE 0x44E10600
+#elif defined(CONFIG_TI814X)
+#define CTRL_BASE 0x48140000
+#endif
/* PRCM Base Address */
+#ifdef CONFIG_AM33XX
#define PRCM_BASE 0x44E00000
+#elif defined(CONFIG_TI814X)
+#define PRCM_BASE 0x48180000
+#endif
+
+/* PLL Subsystem Base Address */
+#ifdef CONFIG_TI814X
+#define PLL_SUBSYS_BASE 0x481C5000
+#endif
/* EMIF Base address */
#define EMIF4_0_CFG_BASE 0x4C000000
@@ -99,10 +123,18 @@
/* CPSW Config space */
#define CPSW_BASE 0x4A100000
+#ifdef CONFIG_AM33XX
#define CPSW_MDIO_BASE 0x4A101000
+#elif defined(CONFIG_TI814X)
+#define CPSW_MDIO_BASE 0x4A100800
+#endif
/* RTC base address */
+#ifdef CONFIG_AM33XX
#define RTC_BASE 0x44E3E000
+#elif defined(CONFIG_TI814X)
+#define RTC_BASE 0x480C0000
+#endif
/* OTG */
#define USB0_OTG_BASE 0x47401000
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h
b/arch/arm/include/asm/arch-am33xx/omap.h
index 850f8a5..ba4f6d2 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -23,13 +23,20 @@
#ifndef _OMAP_H_
#define _OMAP_H_
+#include <config.h>
+
/*
* Non-secure SRAM Addresses
* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
* at 0x40304000(EMU base) so that our code works for both EMU and GP
*/
+#ifdef CONFIG_AM33XX
#define NON_SECURE_SRAM_START 0x40304000
#define NON_SECURE_SRAM_END 0x4030E000
+#elif defined(CONFIG_TI814X)
+#define NON_SECURE_SRAM_START 0x40300000
+#define NON_SECURE_SRAM_END 0x40320000
+#endif
/* ROM code defines */
/* Boot device */
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h
b/arch/arm/include/asm/arch-am33xx/spl.h
index 644ff35..9b5fe9e 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -25,8 +25,13 @@
#define BOOT_DEVICE_XIP 2
#define BOOT_DEVICE_NAND 5
+#ifdef CONFIG_AM33XX
#define BOOT_DEVICE_MMC1 8
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
+#elif defined(CONFIG_TI814X)
+#define BOOT_DEVICE_MMC1 9
+#define BOOT_DEVICE_MMC2 8 /* ROM only supports 2nd instance */
+#endif
#define BOOT_DEVICE_SPI 11
#define BOOT_DEVICE_UART 65
#define BOOT_DEVICE_CPGMAC 70
--
1.7.9.5
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