On Wed, Feb 13, 2013 at 12:59:05PM +0530, Lokesh Vutla wrote: > A new DPLL DDR is added in DRA7XX socs. Now clocks to > EMIF CD is from DPLL DDR. So DPLL DDR should be locked > before initializing RAM. > Also adding other dpll data which are different from OMAP5 ES2.0. > SYS_CLK running at 20MHz is introduced in DRA7xx socs. > > Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com> > Signed-off-by: R Sricharan <r.sricha...@ti.com>
Reviewed-by: Tom Rini <tr...@ti.com> -- Tom
signature.asc
Description: Digital signature
_______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
