Dear Benoît Thébaudeau,
> On Monday, February 25, 2013 7:19:55 PM, Marek Vasut wrote:
> > The MX53 ROM loads the data from NAND in multiples of pages and
> > supports maximum page size of 4k. Thus, align the image and header
> > to 4k to be safe from ROM bugs.
> >
> > Signed-off-by: Marek Vasut <ma...@denx.de>
> > Cc: Benoît Thébaudeau <benoit.thebaud...@advansee.com>
> > Cc: Fabio Estevam <fabio.este...@freescale.com>
> > Cc: Stefano Babic <sba...@denx.de>
> > ---
> >
> > tools/imximage.c | 11 +++++++----
> > tools/imximage.h | 3 ++-
> > 2 files changed, 9 insertions(+), 5 deletions(-)
> >
> > diff --git a/tools/imximage.c b/tools/imximage.c
> > index fa308c9..c018562 100644
> > --- a/tools/imximage.c
> > +++ b/tools/imximage.c
> > @@ -518,11 +518,14 @@ static void imximage_set_header(void *ptr, struct
> > stat *sbuf, int ifd,
> >
> > /*
> >
> > * ROM bug alert
> >
> > - * mx53 only loads 512 byte multiples.
> > - * The remaining fraction of a block bytes would
> > - * not be loaded.
> > + *
> > + * MX53 only loads 512 byte multiples in case of SD boot.
> > + * MX53 only loads NAND page multiples in case of NAND boot and
> > + * supports up to 4096 byte large pages, thus align to 4096.
> > + *
> > + * The remaining fraction of a block bytes would not be loaded!
> >
> > */
> >
> > - *header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 512);
> > + *header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 4096);
> >
> > }
> >
> > int imximage_check_params(struct mkimage_params *params)
> >
> > diff --git a/tools/imximage.h b/tools/imximage.h
> > index 42b6090..dfd2e9e 100644
> > --- a/tools/imximage.h
> > +++ b/tools/imximage.h
> > @@ -151,13 +151,14 @@ typedef struct {
> >
> > dcd_v2_t dcd_table;
> >
> > } imx_header_v2_t;
> >
> > +/* The header must be aligned to 4k on MX53 for NAND boot */
> >
> > struct imx_header {
> >
> > union {
> >
> > imx_header_v1_t hdr_v1;
> > imx_header_v2_t hdr_v2;
> >
> > } header;
> > uint32_t flash_offset;
> >
> > -};
> > +} __attribute__((aligned(4096)));
>
> So what is the exact rule for the image start page in the FCB? Is it just
> 0x400 + 4096 + start page * page size? This does not seem to match table
> 7-12, unless 0 has a special meaning?
I believe it's '0 == offset 4096 in NAND', do you happen to have board with 4k
page NAND to verify this?
> > typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
> >
> > char *name, int lineno,
> >
> > --
> > 1.7.10.4
>
> Best regards,
> Benoît
Best regards,
Marek Vasut
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