[U-Boot] [PATCH] spi: mxc_spi: Set master mode for all channels

[Fabio Estevam]

From: Fabio Estevam <fabio.este...@freescale.com>

The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by 
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling).

Actually the glitch is happening due to always toggling between slave mode
and master mode by configuring the CHANNEL_MODE bits in this reset function.

Since the spi driver only supports master mode, set the mode for all channels 
always to master mode in order to have a stable, "glitch-free" SPI clock line.

Signed-off-by: Fabio Estevam <fabio.este...@freescale.com>
---
 drivers/spi/mxc_spi.c |   11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 4c19e0b..9eb2bce 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -137,9 +137,14 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, 
unsigned int cs,
                return -1;
        }
 
-       /* Reset spi */
-       reg_write(&regs->ctrl, 0);
-       reg_write(&regs->ctrl, MXC_CSPICTRL_EN);
+       /*
+        * Reset SPI and set all CSs to master mode, if toggling
+        * between slave and master mode we might see a glitch
+        * on the clock line
+        */
+       reg_write(&regs->ctrl, 0x000000F0);
+       reg_ctrl = reg_read(&regs->ctrl);
+       reg_write(&regs->ctrl, reg_ctrl | MXC_CSPICTRL_EN);
 
        reg_ctrl = reg_read(&regs->ctrl);
 
-- 
1.7.9.5

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