There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR
in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then
invalidate it after LBCR bit 13 is set.
Signed-off-by: Haiying Wang <haiying.w...@freescale.com>
---
cpu/mpc85xx/Makefile | 1 +
cpu/mpc85xx/cpu.c | 2 +
cpu/mpc85xx/start.S | 49 ++++++++++++++++++++++++++++++++++++++++++
drivers/misc/fsl_law.c | 2 +-
include/asm-ppc/immap_85xx.h | 13 ++++++++++-
include/asm-ppc/immap_qe.h | 8 ++++--
include/asm-ppc/processor.h | 2 +
7 files changed, 72 insertions(+), 5 deletions(-)
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index 99d88a8..8809302 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -49,6 +49,7 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
+COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 5b72fe5..ef976a4 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -61,6 +61,8 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8567, 8567_E),
CPU_TYPE_ENTRY(8568, 8568),
CPU_TYPE_ENTRY(8568, 8568_E),
+ CPU_TYPE_ENTRY(8569, 8569),
+ CPU_TYPE_ENTRY(8569, 8569_E),
CPU_TYPE_ENTRY(8572, 8572),
CPU_TYPE_ENTRY(8572, 8572_E),
CPU_TYPE_ENTRY(P2020, P2020),
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 80f9677..0424b2b 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -184,6 +184,55 @@ _start_e500:
mtspr DBCR0,r0
#endif
+#ifdef CONFIG_MPC8569
+#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
+#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
+
+ /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
+ * use address space which is more than 12bits, and it must be done in
+ * the 4K boot page. So we set this bit here.
+ */
+
+ /* create a temp mapping TLB0[0] for LBCR */
+ lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
+ ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
+
+ lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
+ ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
+
+ lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
+ ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
+
+ lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))@l
+
+ mtspr MAS0,r6
+ mtspr MAS1,r7
+ mtspr MAS2,r8
+ mtspr MAS3,r9
+ isync
+ msync
+ tlbwe
+
+ /* Set LBCR register */
+ lis r4,config_sys_lbcr_a...@h
+ ori r4,r4,config_sys_lbcr_a...@l
+
+ lis r5,config_sys_lbc_l...@h
+ ori r5,r5,config_sys_lbc_l...@l
+ stw r5,0(r4)
+ isync
+
+ /* invalidate this temp TLB */
+ lis r4,config_sys_lbc_a...@h
+ ori r4,r4,config_sys_lbc_a...@l
+ tlbivax 0,r4
+ isync
+
+#endif /* CONFIG_MPC8569 */
+
/* create a temp mapping in AS=1 to the 4M boot window */
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index 58340c1..be43a3e 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
#define FSL_HW_NUM_LAWS 8
#elif defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
- defined(CONFIG_MPC8568) || \
+ defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569) || \
defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
#define FSL_HW_NUM_LAWS 10
#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 094fb9c..0810b8e 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1609,8 +1609,19 @@ typedef struct ccsr_gur {
char res2[12];
uint gpiocr; /* 0xe0030 - GPIO control register */
char res3[12];
+#if defined(CONFIG_MPC8569)
+ uint plppar1;
+ /* 0xe0040 - Platform port pin assignment register 1 */
+ uint plppar2;
+ /* 0xe0044 - Platform port pin assignment register 2 */
+ uint plpdir1;
+ /* 0xe0048 - Platform port pin direction register 1 */
+ uint plpdir2;
+ /* 0xe004c - Platform port pin direction register 2 */
+#else
uint gpoutdr; /* 0xe0040 - General-purpose output data
register */
char res4[12];
+#endif
uint gpindr; /* 0xe0050 - General-purpose input data
register */
char res5[12];
uint pmuxcr; /* 0xe0060 - Alternate function signal
multiplex control */
@@ -1651,7 +1662,7 @@ typedef struct ccsr_gur {
uint svr; /* 0xe00a4 - System version register */
char res10a[8];
uint rstcr; /* 0xe00b0 - Reset control register */
-#ifdef CONFIG_MPC8568
+#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
char res10b[76];
par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
char res10c[3136];
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 39da377..66a4735 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -20,7 +20,9 @@
typedef struct qe_iram {
u32 iadd; /* I-RAM Address Register */
u32 idata; /* I-RAM Data Register */
- u8 res0[0x78];
+ u8 res0[0x4];
+ u32 iready;
+ u8 res1[0x70];
} __attribute__ ((packed)) qe_iram_t;
/* QE Interrupt Controller
@@ -580,7 +582,7 @@ typedef struct qe_immap {
u8 res14[0x300];
u8 res15[0x3A00];
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
-#if defined(CONFIG_MPC8568)
+#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
#else
@@ -592,7 +594,7 @@ typedef struct qe_immap {
extern qe_map_t *qe_immr;
-#if defined(CONFIG_MPC8568)
+#if defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569)
#define QE_MURAM_SIZE 0x10000UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 5b29de0..83e3581 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -955,6 +955,8 @@
#define SVR_8567_E 0x807E00
#define SVR_8568 0x807500
#define SVR_8568_E 0x807D00
+#define SVR_8569 0x808000
+#define SVR_8569_E 0x808800
#define SVR_8572 0x80E000
#define SVR_8572_E 0x80E800
#define SVR_P2020 0x80E200
--
1.6.0.2
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