Mark, On Tue, Apr 16, 2013 at 20:32:34, Mark Jackson wrote: > NanoBone Specification: > ----------------------- > Memory: > 256MB DDR3 > 64MB NOR flash > 256MB NAND flash > 128KB FRAM > > Ethernet: > 2 x 10/100 connected to SMSC LAN8710 PHY > > USB: > 1 x USB2.0 Type A > > I2C: > 2Kbit EEPROM (Microchip 24AA02) > RTC (Maxim DS1338) > GPIO Expander (Microchip MCP23017) > > Expansion connector: > 6 x UART > 1 x MMC/SD > 1 x USB2.0 > > Signed-off-by: Mark Jackson <m...@newflow.co.uk> > --- > MAINTAINERS | 4 + > board/newflow/nanobone/Makefile | 46 ++++++ > board/newflow/nanobone/board.c | 337 > +++++++++++++++++++++++++++++++++++++++ > board/newflow/nanobone/board.h | 24 +++ > board/newflow/nanobone/mux.c | 203 +++++++++++++++++++++++ > boards.cfg | 1 + > include/configs/nanobone.h | 291 +++++++++++++++++++++++++++++++++ > 7 files changed, 906 insertions(+) > create mode 100644 board/newflow/nanobone/Makefile > create mode 100644 board/newflow/nanobone/board.c > create mode 100644 board/newflow/nanobone/board.h > create mode 100644 board/newflow/nanobone/mux.c > create mode 100644 include/configs/nanobone.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 1614b91..7778883 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -710,6 +710,10 @@ Ilko Iliev <il...@ronetix.at> > PM9263 AT91SAM9263 > PM9G45 ARM926EJS (AT91SAM9G45 SoC) > > +Mark Jackson <m...@newflow.co.uk>
A small nit-pick, you sent the commit using email id as "mpfj-l...@mimc.co.uk" But in the maintainer file, it shows as "m...@newflow.co.uk". Is this valid/correct? Regards Gururaja > + > + NANOBONE ARM ARMV7 (AM33xx Soc) > + > Michael Jones <michael.jo...@matrix-vision.de> > > omap3_mvblx ARM ARMV7 (OMAP3xx SoC) > diff --git a/board/newflow/nanobone/Makefile b/board/newflow/nanobone/Makefile > new file mode 100644 > index 0000000..67a87a1 > --- /dev/null > +++ b/board/newflow/nanobone/Makefile > @@ -0,0 +1,46 @@ > +# > +# Makefile > +# > +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed "as is" WITHOUT ANY WARRANTY of any > +# kind, whether express or implied; without even the implied warranty > +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(BOARD).o > + > +ifdef CONFIG_SPL_BUILD > +COBJS := mux.o > +endif > + > +COBJS += board.o > +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS)) > +SOBJS := $(addprefix $(obj),$(SOBJS)) > + > +$(LIB): $(obj).depend $(OBJS) $(SOBJS) > + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) > + > +clean: > + rm -f $(SOBJS) $(OBJS) > + > +distclean: clean > + rm -f $(LIB) core *.bak $(obj).depend > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/board/newflow/nanobone/board.c b/board/newflow/nanobone/board.c > new file mode 100644 > index 0000000..e8f7e00 > --- /dev/null > +++ b/board/newflow/nanobone/board.c > @@ -0,0 +1,337 @@ > +/* > + * board.c > + * > + * Board functions for Newflow NanoBone board > + * > + * Copyright (C) 2013, Newflow Ltd - http://www.newflow.co.uk/ > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <common.h> > +#include <errno.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/cpu.h> > +#include <asm/arch/ddr_defs.h> > +#include <asm/arch/gpio.h> > +#include <asm/arch/hardware.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/arch/mem.h> > +#include <asm/arch/mmc_host_def.h> > +#include <asm/arch/omap.h> > +#include <asm/emif.h> > +#include <asm/gpio.h> > +#include <asm/io.h> > +#include <cpsw.h> > +#include <i2c.h> > +#include <miiphy.h> > +#include <spl.h> > +#include "board.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +/* FRAM config */ > +#define FRAM_CS 1 > +#define FRAM_BASE 0x1c000000 > +#define FRAM_SIZE GPMC_SIZE_16M > +static u32 gpmc_fram_config[GPMC_MAX_REG] = { > + 0x00001200, > + 0x00101000, > + 0x00020201, > + 0x0f030f03, > + 0x010d1010, > + 0x000301c0, > + 0 > +}; > + > +/* NOR Flash config */ > +#define NOR_CS 3 > +#define NOR_BASE 0x18000000 > +#define NOR_SIZE GPMC_SIZE_64M > +static u32 gpmc_nor_config[GPMC_MAX_REG] = { > + 0x00001200, > + 0x00101004, > + 0x00020201, > + 0x10041004, > + 0x010f1010, > + 0x000601c0, > + 0 > +}; > + > +static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; > +#ifdef CONFIG_SPL_BUILD > +static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; > +#endif > + > +/* MII mode defines */ > +#define PORT1_MII_MODE_ENABLE 0x0 > +#define PORT2_MII_MODE_ENABLE 0x0 > + > +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; > + > +/* UART Defines */ > +#ifdef CONFIG_SPL_BUILD > +#define UART_RESET (0x1 << 1) > +#define UART_CLK_RUNNING_MASK 0x1 > +#define UART_SMART_IDLE_EN (0x1 << 0x3) > + > +static void rtc32k_enable(void) > +{ > + struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; > + > + /* > + * Unlock the RTC's registers. For more details please see the > + * RTC_SS section of the TRM. In order to unlock we need to > + * write these specific values (keys) in this order. > + */ > + writel(0x83e70b13, &rtc->kick0r); > + writel(0x95a4f1e0, &rtc->kick1r); > + > + /* Enable the RTC 32K OSC by setting bits 3 and 6. */ > + writel((1 << 3) | (1 << 6), &rtc->osc); > +} > + > +static const struct ddr_data ddr3_data = { > + .datardsratio0 = MT41J128MJT125_RD_DQS, > + .datawdsratio0 = MT41J128MJT125_WR_DQS, > + .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, > + .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, > + .datadldiff0 = PHY_DLL_LOCK_DIFF, > +}; > + > +static const struct cmd_control ddr3_cmd_ctrl_data = { > + .cmd0csratio = MT41J128MJT125_RATIO, > + .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, > + .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, > + > + .cmd1csratio = MT41J128MJT125_RATIO, > + .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, > + .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, > + > + .cmd2csratio = MT41J128MJT125_RATIO, > + .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, > + .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, > +}; > + > +static struct emif_regs ddr3_emif_reg_data = { > + .sdram_config = MT41J128MJT125_EMIF_SDCFG, > + .ref_ctrl = MT41J128MJT125_EMIF_SDREF, > + .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, > + .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, > + .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, > + .zq_config = MT41J128MJT125_ZQ_CFG, > + .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY, > +}; > +#endif /* CONFIG_SPL_BUILD */ > + > +#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD) > +/****************************************************************************** > + * OMAP3 specific command to switch between NAND HW and SW ecc > + > *****************************************************************************/ > +static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const > argv[]) > +{ > + if (argc < 2) > + goto usage; > + if (strncmp(argv[1], "hw", 2) == 0) > + { > + int type = 1; > + if (argc == 3) > + type = simple_strtoul(argv[2], NULL, 10); > + omap_nand_switch_ecc(type); > + } > + else if (strncmp(argv[1], "sw", 2) == 0) > + omap_nand_switch_ecc(0); > + else > + goto usage; > + > + return 0; > + > +usage: > + printf ("Usage: nandecc %s\n", cmdtp->usage); > + return 1; > +} > + > +U_BOOT_CMD( > + nandecc, 3, 1, do_switch_ecc, > + "switch OMAP3 NAND ECC calculation algorithm", > + "[hw 1/hw 2/sw] - Switch between NAND ecc algorithm\n" > + " hw 1 = kernel/FS layout\n" > + " hw 2 = xloader/uboot layout\n" > + " sw = 1-bit software" > +); > + > +#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ > + > +/* > + * early system init of muxing and clocks. > + */ > +void s_init(void) > +{ > + /* WDT1 is already running when the bootloader gets control > + * Disable it to avoid "random" resets > + */ > + writel(0xAAAA, &wdtimer->wdtwspr); > + while (readl(&wdtimer->wdtwwps) != 0x0) > + ; > + writel(0x5555, &wdtimer->wdtwspr); > + while (readl(&wdtimer->wdtwwps) != 0x0) > + ; > + > +#ifdef CONFIG_SPL_BUILD > + /* Setup the PLLs and the clocks for the peripherals */ > + pll_init(); > + > + /* Enable RTC32K clock */ > + rtc32k_enable(); > + > + /* UART softreset */ > + u32 regVal; > + regVal = readl(&uart_base->uartsyscfg); > + regVal |= UART_RESET; > + writel(regVal, &uart_base->uartsyscfg); > + while ((readl(&uart_base->uartsyssts) & > + UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) > + ; > + > + /* Disable smart idle */ > + regVal = readl(&uart_base->uartsyscfg); > + regVal |= UART_SMART_IDLE_EN; > + writel(regVal, &uart_base->uartsyscfg); > + > + config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, > + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); > + > + gd = &gdata; > + > + enable_board_pin_mux(); > + > + preloader_console_init(); > + > + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); > +#endif /* CONFIG_SPL_BUILD */ > +} > + > +/* > + * Basic board specific setup. Pinmux has been handled already. > + */ > +int board_init(void) > +{ > + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); > + > + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; > + > + gpmc_init(); > + > + /* enable FRAM chip select */ > + enable_gpmc_cs_config(gpmc_fram_config, &gpmc_cfg->cs[FRAM_CS], > + FRAM_BASE, FRAM_SIZE); > + /* enable NOR flash chip select */ > + enable_gpmc_cs_config(gpmc_nor_config, &gpmc_cfg->cs[NOR_CS], > + NOR_BASE, NOR_SIZE); > + > + return 0; > +} > + > +int board_late_init(void) > +{ > + setenv("board_name", "nanobone"); > + setenv("board_rev", "0001"); > + > + return 0; > +} > + > +static void cpsw_control(int enabled) > +{ > + /* VTP can be added here */ > + > + return; > +} > + > +static struct cpsw_slave_data cpsw_slaves[] = { > + { > + .slave_reg_ofs = 0x208, > + .sliver_reg_ofs = 0xd80, > + .phy_id = 0, > + }, > + { > + .slave_reg_ofs = 0x308, > + .sliver_reg_ofs = 0xdc0, > + .phy_id = 1, > + }, > +}; > + > +static struct cpsw_platform_data cpsw_data = { > + .mdio_base = CPSW_MDIO_BASE, > + .cpsw_base = CPSW_BASE, > + .mdio_div = 0xff, > + .channels = 8, > + .cpdma_reg_ofs = 0x800, > + .slaves = 2, > + .slave_data = cpsw_slaves, > + .ale_reg_ofs = 0xd00, > + .ale_entries = 1024, > + .host_port_reg_ofs = 0x108, > + .hw_stats_reg_ofs = 0x900, > + .mac_control = (1 << 5), > + .control = cpsw_control, > + .host_port_num = 0, > + .version = CPSW_CTRL_VERSION_2, > +}; > + > +int board_eth_init(bd_t *bis) > +{ > + int rv, n = 0; > + uint8_t mac_addr[6]; > + uint32_t mac_hi, mac_lo; > + > + if (!getenv("ethaddr")) { > + printf("<ethaddr> not set. Reading from E-fuse\n"); > + /* try reading mac address from efuse */ > + mac_lo = readl(&cdev->macid0l); > + mac_hi = readl(&cdev->macid0h); > + mac_addr[0] = mac_hi & 0xff; > + mac_addr[1] = (mac_hi & 0xff00) >> 8; > + mac_addr[2] = (mac_hi & 0xff0000) >> 16; > + mac_addr[3] = (mac_hi & 0xff000000) >> 24; > + mac_addr[4] = mac_lo & 0xff; > + mac_addr[5] = (mac_lo & 0xff00) >> 8; > + > + if (is_valid_ether_addr(mac_addr)) > + eth_setenv_enetaddr("ethaddr", mac_addr); > + } > + > + if (!getenv("eth1addr")) { > + printf("<eth1addr> not set. Reading from E-fuse\n"); > + /* try reading mac address from efuse */ > + mac_lo = readl(&cdev->macid1l); > + mac_hi = readl(&cdev->macid1h); > + mac_addr[0] = mac_hi & 0xff; > + mac_addr[1] = (mac_hi & 0xff00) >> 8; > + mac_addr[2] = (mac_hi & 0xff0000) >> 16; > + mac_addr[3] = (mac_hi & 0xff000000) >> 24; > + mac_addr[4] = mac_lo & 0xff; > + mac_addr[5] = (mac_lo & 0xff00) >> 8; > + > + if (is_valid_ether_addr(mac_addr)) > + eth_setenv_enetaddr("eth1addr", mac_addr); > + } > + > + writel(PORT1_MII_MODE_ENABLE | PORT2_MII_MODE_ENABLE, &cdev->miisel); > + cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; > + > + rv = cpsw_register(&cpsw_data); > + if (rv < 0) > + printf("Error %d registering CPSW switch\n", rv); > + else > + n += rv; > + > + return n; > +} > diff --git a/board/newflow/nanobone/board.h b/board/newflow/nanobone/board.h > new file mode 100644 > index 0000000..9f5075b > --- /dev/null > +++ b/board/newflow/nanobone/board.h > @@ -0,0 +1,24 @@ > +/* > + * board.h > + * > + * TI AM335x boards information header > + * > + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#ifndef _BOARD_H_ > +#define _BOARD_H_ > + > +void enable_board_pin_mux(void); > + > +#endif > diff --git a/board/newflow/nanobone/mux.c b/board/newflow/nanobone/mux.c > new file mode 100644 > index 0000000..bf9c999 > --- /dev/null > +++ b/board/newflow/nanobone/mux.c > @@ -0,0 +1,203 @@ > +/* > + * mux.c > + * > + * Copyright (C) 2013, Newflow Ltd - http://www.newflow.co.uk/ > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation version 2. > + * > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any > + * kind, whether express or implied; without even the implied warranty > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <common.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/arch/hardware.h> > +#include <asm/arch/mux.h> > +#include <asm/io.h> > +#include <i2c.h> > +#include "board.h" > + > +static struct module_pin_mux gpmc_pin_mux[] = { > + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD0 */ > + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD1 */ > + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD2 */ > + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD3 */ > + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD4 */ > + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD5 */ > + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD6 */ > + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD7 */ > + {OFFSET(gpmc_ad8), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD8 */ > + {OFFSET(gpmc_ad9), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD9 */ > + {OFFSET(gpmc_ad10), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD10 */ > + {OFFSET(gpmc_ad11), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD11 */ > + {OFFSET(gpmc_ad12), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD12 */ > + {OFFSET(gpmc_ad13), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD13 */ > + {OFFSET(gpmc_ad14), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD14 */ > + {OFFSET(gpmc_ad15), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD15 */ > + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* GPMC_CSN0 */ > + {OFFSET(gpmc_csn1), (MODE(0) | PULLUDEN)}, /* GPMC_CSN1 */ > + {OFFSET(gpmc_csn2), (MODE(0) | PULLUDEN)}, /* GPMC_CSN2 */ > + {OFFSET(gpmc_csn3), (MODE(0) | PULLUDEN)}, /* GPMC_CSN3 */ > + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* GPMC_ADV_ALE */ > + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* GPMC_OE */ > + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* GPMC_WEN */ > + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* GPMC_BE_CLE */ > + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE)}, /* NAND WAIT */ > + {OFFSET(lcd_data1), (MODE(1) | PULLUDDIS)}, /* GPMC A17 */ > + {OFFSET(lcd_data2), (MODE(1) | PULLUDDIS)}, /* GPMC A18 */ > + {OFFSET(lcd_data3), (MODE(1) | PULLUDDIS)}, /* GPMC A19 */ > + {OFFSET(lcd_data4), (MODE(1) | PULLUDDIS)}, /* GPMC A20 */ > + {OFFSET(lcd_data5), (MODE(1) | PULLUDDIS)}, /* GPMC A21 */ > + {OFFSET(lcd_data6), (MODE(1) | PULLUDDIS)}, /* GPMC A22 */ > + {OFFSET(lcd_data7), (MODE(1) | PULLUDDIS)}, /* GPMC A23 */ > + {OFFSET(lcd_data8), (MODE(1) | PULLUDDIS)}, /* GPMC A24 */ > + {OFFSET(lcd_data9), (MODE(1) | PULLUDDIS)}, /* GPMC A25 */ > + {OFFSET(lcd_data10), (MODE(1) | PULLUDDIS)}, /* GPMC A26 */ > + {-1}, > +}; > + > +static struct module_pin_mux i2c0_pin_mux[] = { > + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | > + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ > + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | > + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ > + {-1}, > +}; > + > +static struct module_pin_mux mii1_pin_mux[] = { > + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ > + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ > + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ > + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ > + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ > + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ > + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ > + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ > + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ > + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ > + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ > + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ > + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ > + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ > + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ > + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ > + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ > + {-1}, > +}; > + > +static struct module_pin_mux mii2_pin_mux[] = { > + {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */ > + {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */ > + {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */ > + {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */ > + {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */ > + {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */ > + {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */ > + {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */ > + {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */ > + {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */ > + {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ > + {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ > + {OFFSET(gpmc_wpn), MODE(1) | RXACTIVE}, /* MII2_RXERR */ > + {OFFSET(gpmc_be1n), MODE(1) | RXACTIVE}, /* MII2_COL */ > + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ > + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ > + {-1}, > +}; > + > +static struct module_pin_mux mmc0_no_cd_pin_mux[] = { > + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ > + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ > + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ > + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ > + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ > + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ > + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ > + {OFFSET(emu1), (MODE(7) | RXACTIVE)}, /* MMC0_CD */ > + {-1}, > +}; > + > +static struct module_pin_mux uart0_pin_mux[] = { > + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ > + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ > + {-1}, > +}; > + > +static struct module_pin_mux uart1_pin_mux[] = { > + {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_CTSN */ > + {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)}, /* UART1_RTSN */ > + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ > + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ > + {-1}, > +}; > + > +static struct module_pin_mux uart2_pin_mux[] = { > + {OFFSET(lcd_data8), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART2_CTSN */ > + {OFFSET(lcd_data9), (MODE(6) | PULLUDEN)}, /* UART2_RTSN */ > + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ > + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ > + {-1}, > +}; > + > +static struct module_pin_mux uart3_pin_mux[] = { > + {OFFSET(lcd_data10), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART3_CTSN */ > + {OFFSET(lcd_data11), (MODE(6) | PULLUDEN)}, /* UART3_RTSN */ > + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ > + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ > + {-1}, > +}; > + > +static struct module_pin_mux uart4_pin_mux[] = { > + {OFFSET(lcd_data12), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_CTSN */ > + {OFFSET(lcd_data13), (MODE(6) | PULLUDEN)}, /* UART4_RTSN */ > + {OFFSET(uart0_ctsn), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ > + {OFFSET(uart0_rtsn), (MODE(1) | PULLUDEN)}, /* UART4_TXD */ > + {-1}, > +}; > + > +static struct module_pin_mux uart5_pin_mux[] = { > + {OFFSET(lcd_data14), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ > + {OFFSET(rmii1_refclk), (MODE(3) | PULLUDEN)}, /* UART5_TXD */ > + {-1}, > +}; > + > +static struct module_pin_mux usb0_pin_mux[] = { > + {OFFSET(usb0_dm), (MODE(0) | RXACTIVE)}, /* USB0_DM */ > + {OFFSET(usb0_dp), (MODE(0) | RXACTIVE)}, /* USB0_DP */ > + {OFFSET(usb0_ce), (MODE(0) | RXACTIVE)}, /* USB0_CE */ > + {OFFSET(usb0_id), (MODE(0) | RXACTIVE)}, /* USB0_ID */ > + {OFFSET(usb0_vbus), (MODE(0) | RXACTIVE)}, /* USB0_VBUS */ > + {OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)}, /* USB0_DRVVBUS */ > + {-1}, > +}; > + > +static struct module_pin_mux usb1_pin_mux[] = { > + {OFFSET(usb1_dm), (MODE(0) | RXACTIVE)}, /* USB1_DM */ > + {OFFSET(usb1_dp), (MODE(0) | RXACTIVE)}, /* USB1_DP */ > + {OFFSET(usb1_ce), (MODE(0) | RXACTIVE)}, /* USB1_CE */ > + {OFFSET(usb1_id), (MODE(0) | RXACTIVE)}, /* USB1_ID */ > + {OFFSET(usb1_vbus), (MODE(0) | RXACTIVE)}, /* USB1_VBUS */ > + {OFFSET(usb1_drvvbus), (MODE(0) | PULLUDEN)}, /* USB1_DRVVBUS */ > + {-1}, > +}; > + > +void enable_board_pin_mux() > +{ > + configure_module_pin_mux(gpmc_pin_mux); > + configure_module_pin_mux(i2c0_pin_mux); > + configure_module_pin_mux(mii1_pin_mux); > + configure_module_pin_mux(mii2_pin_mux); > + configure_module_pin_mux(mmc0_no_cd_pin_mux); > + configure_module_pin_mux(uart0_pin_mux); > + configure_module_pin_mux(uart1_pin_mux); > + configure_module_pin_mux(uart2_pin_mux); > + configure_module_pin_mux(uart3_pin_mux); > + configure_module_pin_mux(uart4_pin_mux); > + configure_module_pin_mux(uart5_pin_mux); > + configure_module_pin_mux(usb0_pin_mux); > + configure_module_pin_mux(usb1_pin_mux); > +} > diff --git a/boards.cfg b/boards.cfg > index 5fc70be..b2f68e9 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -241,6 +241,7 @@ am335x_evm_uart3 arm armv7 > am335x ti > am335x_evm_uart4 arm armv7 am335x ti > am33xx am335x_evm:SERIAL5,CONS_INDEX=5 > am335x_evm_uart5 arm armv7 am335x ti > am33xx am335x_evm:SERIAL6,CONS_INDEX=6 > am335x_evm_usbspl arm armv7 am335x ti > am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT > +nanobone arm armv7 nanobone > newflow am33xx > ti814x_evm arm armv7 ti814x ti > am33xx > pcm051 arm armv7 pcm051 > phytec am33xx pcm051 > highbank arm armv7 highbank - > highbank > diff --git a/include/configs/nanobone.h b/include/configs/nanobone.h > new file mode 100644 > index 0000000..184f06a > --- /dev/null > +++ b/include/configs/nanobone.h > @@ -0,0 +1,291 @@ > +/* > + * nanobone.h > + * > + * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation version 2. > + * > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any > + * kind, whether express or implied; without even the implied warranty > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#ifndef __CONFIG_NANOBONE_H > +#define __CONFIG_NANOBONE_H > + > +#define CONFIG_AM33XX > + > +#include <asm/arch/omap.h> > + > +#define CONFIG_DMA_COHERENT > +#define CONFIG_DMA_COHERENT_SIZE (1 << 20) > + > +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ > +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) > +#define CONFIG_SYS_LONGHELP /* undef to save memory */ > +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ > +#define CONFIG_SYS_PROMPT "U-Boot# " > +#define CONFIG_BOARD_LATE_INIT > +#define CONFIG_SYS_NO_FLASH > +#define MACH_TYPE_NANOBONE 4483 > +#define CONFIG_MACH_TYPE MACH_TYPE_NANOBONE > + > +#define CONFIG_OF_LIBFDT > +#define CONFIG_CMD_BOOTZ > +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ > +#define CONFIG_SETUP_MEMORY_TAGS > +#define CONFIG_INITRD_TAG > + > +/* commands to include */ > +#include <config_cmd_default.h> > + > +#define CONFIG_CMD_ASKENV > +#define CONFIG_VERSION_VARIABLE > + > +/* set to negative value for no autoboot */ > +#define CONFIG_BOOTDELAY 0 > +#define CONFIG_ZERO_BOOTDELAY_CHECK > +#define CONFIG_ENV_VARS_UBOOT_CONFIG > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG > +#ifndef CONFIG_SPL_BUILD > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "loadaddr=0x80200000\0" \ > + "fdtaddr=0x80f80000\0" \ > + "fdt_high=0xffffffff\0" \ > + "console=ttyO0,115200n8\0" \ > + > +#endif /* CONFIG_SPL_BUILD */ > + > +#define CONFIG_BOOTCOMMAND "mtdparts default; " \ > + "nand read $loadaddr kernel; bootm" > +#define CONFIG_BOOTARGS "console=ttyO0,115200n8 noinitrd ip=off > " \ > + "mem=256M rootwait=1 ubi.mtd=4,2048 " \ > + "rootfstype=ubifs root=ubi0:rootfs " \ > + "ignore_loglevel" > + > +/* Clock Defines */ > +#define V_OSCK 26000000 /* Clock output from > T2 */ > +#define V_SCLK (V_OSCK) > +#define CONFIG_SYS_MPUCLK 720 > + > +#define CONFIG_CMD_ECHO > + > +/* max number of command args */ > +#define CONFIG_SYS_MAXARGS 16 > + > +/* Console I/O Buffer Size */ > +#define CONFIG_SYS_CBSIZE 512 > + > +/* Print Buffer Size */ > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ > + + sizeof(CONFIG_SYS_PROMPT) + 16) > + > +/* Boot Argument Buffer Size */ > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > + > +/* > + * memtest works on 8 MB in DRAM after skipping 32MB from > + * start addr of ram disk > + */ > +#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) > +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ > + + (8 * 1024 * 1024)) > + > +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ > +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ > + > +#define CONFIG_MMC > +#define CONFIG_GENERIC_MMC > +#define CONFIG_OMAP_HSMMC > +#define CONFIG_CMD_MMC > +#define CONFIG_DOS_PARTITION > +#define CONFIG_CMD_FAT > +#define CONFIG_CMD_EXT2 > +#define CONFIG_CMD_EXT4 > +#define CONFIG_CMD_FS_GENERIC > + > + /* Physical Memory Map */ > +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ > +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ > +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ > + > +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 > +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ > + GENERATED_GBL_DATA_SIZE) > + /* Platform/Board specific defs */ > +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ > +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) > => 8 */ > +#define CONFIG_SYS_HZ 1000 > + > +/* NS16550 Configuration */ > +#define CONFIG_SYS_NS16550 > +#define CONFIG_SYS_NS16550_SERIAL > +#define CONFIG_SERIAL_MULTI > +#define CONFIG_SYS_NS16550_REG_SIZE (-4) > +#define CONFIG_SYS_NS16550_CLK (48000000) > +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ > +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ > +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ > +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ > +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ > +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ > +#define CONFIG_CONS_INDEX 1 > + > +/* I2C Configuration */ > +#define CONFIG_I2C > +#define CONFIG_CMD_I2C > +#define CONFIG_HARD_I2C > +#define CONFIG_SYS_I2C_SPEED 100000 > +#define CONFIG_SYS_I2C_SLAVE 1 > +#define CONFIG_I2C_MULTI_BUS > +#define CONFIG_DRIVER_OMAP24XX_I2C > +#define CONFIG_CMD_EEPROM > +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ > +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 > +#define CONFIG_SYS_I2C_MULTI_EEPROMS > + > +#define CONFIG_OMAP_GPIO > + > +#define CONFIG_BAUDRATE 115200 > + > +#define CONFIG_SYS_CONSOLE_INFO_QUIET > + > +/* Defines for SPL */ > +#define CONFIG_SPL > +#define CONFIG_SPL_FRAMEWORK > +#define CONFIG_SPL_TEXT_BASE 0x402F0400 > +#define CONFIG_SPL_MAX_SIZE (101 * 1024) > +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR > + > +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 > +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ > + > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address > 0x60000 */ > +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ > +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 > +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" > +#define CONFIG_SPL_MMC_SUPPORT > +#define CONFIG_SPL_FAT_SUPPORT > +#define CONFIG_SPL_I2C_SUPPORT > + > +#define CONFIG_SPL_LIBCOMMON_SUPPORT > +#define CONFIG_SPL_LIBDISK_SUPPORT > +#define CONFIG_SPL_LIBGENERIC_SUPPORT > +#define CONFIG_SPL_SERIAL_SUPPORT > +#define CONFIG_SPL_GPIO_SUPPORT > +#define CONFIG_SPL_YMODEM_SUPPORT > +#define CONFIG_SPL_NET_SUPPORT > +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" > +#define CONFIG_SPL_ETH_SUPPORT > +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" > + > +#define CONFIG_SPL_BOARD_INIT > +#define CONFIG_SPL_NAND_AM33XX_BCH > +#define CONFIG_SPL_NAND_SUPPORT > +#define CONFIG_SPL_NAND_BASE > +#define CONFIG_SPL_NAND_DRIVERS > +#define CONFIG_SPL_NAND_ECC > +#define CONFIG_SYS_NAND_5_ADDR_CYCLE > +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ > + CONFIG_SYS_NAND_PAGE_SIZE) > +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 > +#define CONFIG_SYS_NAND_OOBSIZE 64 > +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) > +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS > +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ > + 10, 11, 12, 13, 14, 15, 16, 17, \ > + 18, 19, 20, 21, 22, 23, 24, 25, \ > + 26, 27, 28, 29, 30, 31, 32, 33, \ > + 34, 35, 36, 37, 38, 39, 40, 41, \ > + 42, 43, 44, 45, 46, 47, 48, 49, \ > + 50, 51, 52, 53, 54, 55, 56, 57, } > + > +#define CONFIG_SYS_NAND_ECCSIZE 512 > +#define CONFIG_SYS_NAND_ECCBYTES 14 > + > +#define CONFIG_SYS_NAND_ECCSTEPS 4 > +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ > + CONFIG_SYS_NAND_ECCSTEPS) > + > +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE > + > +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 > + > +/* > + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM > + * 64 bytes before this address should be set aside for u-boot.img's > + * header. That is 0x800FFFC0--0x80100000 should not be used for any > + * other needs. > + */ > +#define CONFIG_SYS_TEXT_BASE 0x80800000 > +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 > + > +/* Since SPL did pll and ddr initialization for us, > + * we don't need to do it twice. > + */ > +#ifndef CONFIG_SPL_BUILD > +#define CONFIG_SKIP_LOWLEVEL_INIT > +#endif /* CONFIG_SPL_BUILD */ > + > +/* Unsupported features */ > +#undef CONFIG_USE_IRQ > + > +#define CONFIG_CMD_NET > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_PING > +#define CONFIG_DRIVER_TI_CPSW > +#define CONFIG_MII > +#define CONFIG_BOOTP_DEFAULT > +#define CONFIG_BOOTP_DNS > +#define CONFIG_BOOTP_DNS2 > +#define CONFIG_BOOTP_SEND_HOSTNAME > +#define CONFIG_BOOTP_GATEWAY > +#define CONFIG_BOOTP_SUBNETMASK > +#define CONFIG_NET_RETRY_COUNT 10 > +#define CONFIG_NET_MULTI > +#define CONFIG_PHY_GIGE > +#define CONFIG_PHYLIB > +#define CONFIG_PHY_ADDR 0 > +#define CONFIG_PHY_SMSC > + > + > +/* UBIFS support */ > +#define CONFIG_CMD_UBI > +#define CONFIG_CMD_UBIFS > +#define CONFIG_RBTREE > +#define CONFIG_LZO > + > +/* NAND support */ > +#define CONFIG_NAND > +#define CONFIG_CMD_NAND > +#define CONFIG_CMD_NAND_TRIMFFS > + > +#define CONFIG_MTD_DEVICE > +#define CONFIG_MTD_PARTITIONS > +#define CONFIG_CMD_MTDPARTS > +#define MTDIDS_DEFAULT "nand0=nand" > +#define MTDPARTS_DEFAULT "mtdparts=nand:" \ > + "128k(spl)," \ > + "1792k(boot)," \ > + "128k(env)," \ > + "4m(kernel)," \ > + "64m(rootfs)," \ > + "-(data)" > + > +#define CONFIG_NAND_OMAP_GPMC > +#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 > +#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ > + /* to access nand at */ > + /* CS0 */ > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND > + devices */ > +#undef CONFIG_ENV_IS_NOWHERE > +#define CONFIG_ENV_IS_IN_NAND > +#define CONFIG_ENV_OFFSET 0x1e0000 /* environment starts here */ > +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ > + > +#endif /* ! __CONFIG_NANOBONE_H */ > -- > 1.7.9.5 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
