Hi, Liu Hui,
>-----Original Message-----
>From: Wang Huan-B18965
>Sent: Sunday, April 28, 2013 12:48 PM
>To: Liu Hui-R64343; u-boot@lists.denx.de
>Cc: sba...@denx.de; Estevam Fabio-R49496; TsiChung Liew; Jin Zhengxiong-
>R64188
>Subject: RE: [PATCH 1/5] vybrid: add vybrid CPU support
>
>Hi, Liu Hui:
>
>-----Original Message-----
>From: Liu Hui-R64343
>Sent: Monday, April 15, 2013 11:25 AM
>To: Wang Huan-B18965; u-boot@lists.denx.de
>Cc: sba...@denx.de; Estevam Fabio-R49496; TsiChung Liew; Jin Zhengxiong-
>R64188
>Subject: RE: [PATCH 1/5] vybrid: add vybrid CPU support
>
>>-----Original Message-----
>>From: Wang Huan-B18965
>>Sent: Friday, April 12, 2013 2:54 PM
>>To: u-boot@lists.denx.de
>>Cc: sba...@denx.de; Liu Hui-R64343; Estevam Fabio-R49496; TsiChung Liew;
>>Jin Zhengxiong-R64188
>>Subject: [PATCH 1/5] vybrid: add vybrid CPU support
>>
>>The Vybrid devices are a family of Freescale's latest Dual Single
>>Core offering with ARM Cortex A5 and CM4 based processors for
>>Advanced Connected Radio, Entry Infotainment, and Cluster as well
>>as high end industrial and general purpose applications.
>>
>>This patch adds vybrid CPU support.
>>
>>Signed-off-by: TsiChung Liew <tsicl...@gmail.com>
>>Signed-off-by: Jason Jin <jason....@freescale.com>
>>Signed-off-by: Alison Wang <b18...@freescale.com>
>>---
>> Makefile | 8 +
>> arch/arm/cpu/armv7/vybrid-common/Makefile | 46 ++
>> arch/arm/cpu/armv7/vybrid-common/cpu.c | 127 ++++
>> arch/arm/cpu/armv7/vybrid-common/speed.c | 37 ++
>> arch/arm/cpu/armv7/vybrid-common/timer.c | 140 +++++
>> arch/arm/cpu/armv7/vybrid/Makefile | 45 ++
>> arch/arm/cpu/armv7/vybrid/asm-offsets.c | 70 +++
>> arch/arm/cpu/armv7/vybrid/clock.c | 278 +++++++++
>> arch/arm/cpu/armv7/vybrid/iomux.c | 42 ++
>> arch/arm/cpu/armv7/vybrid/lowlevel_init.S | 128 ++++
>> arch/arm/cpu/armv7/vybrid/soc.c | 42 ++
>> arch/arm/include/asm/arch-vybrid/clock.h | 41 ++
>> arch/arm/include/asm/arch-vybrid/iomux.h | 323 ++++++++++
>> arch/arm/include/asm/arch-vybrid/serial-vybrid.h | 213 +++++++
>> arch/arm/include/asm/arch-vybrid/sys_proto.h | 30 +
>> arch/arm/include/asm/arch-vybrid/timer.h | 405 +++++++++++++
>> arch/arm/include/asm/arch-vybrid/vybrid-pins.h | 88 +++
>> arch/arm/include/asm/arch-vybrid/vybrid-regs.h | 735
>>+++++++++++++++++++++++
>> arch/arm/include/asm/global_data.h | 3 +
>> arch/arm/include/asm/mach-types.h | 56 ++
>> 20 files changed, 2857 insertions(+)
>> create mode 100644 arch/arm/cpu/armv7/vybrid-common/Makefile
>> create mode 100644 arch/arm/cpu/armv7/vybrid-common/cpu.c
>> create mode 100644 arch/arm/cpu/armv7/vybrid-common/speed.c
>> create mode 100644 arch/arm/cpu/armv7/vybrid-common/timer.c
>> create mode 100644 arch/arm/cpu/armv7/vybrid/Makefile
>> create mode 100644 arch/arm/cpu/armv7/vybrid/asm-offsets.c
>> create mode 100644 arch/arm/cpu/armv7/vybrid/clock.c
>> create mode 100644 arch/arm/cpu/armv7/vybrid/iomux.c
>> create mode 100644 arch/arm/cpu/armv7/vybrid/lowlevel_init.S
>> create mode 100644 arch/arm/cpu/armv7/vybrid/soc.c
>> create mode 100644 arch/arm/include/asm/arch-vybrid/clock.h
>> create mode 100644 arch/arm/include/asm/arch-vybrid/iomux.h
>> create mode 100644 arch/arm/include/asm/arch-vybrid/serial-vybrid.h
>> create mode 100644 arch/arm/include/asm/arch-vybrid/sys_proto.h
>> create mode 100644 arch/arm/include/asm/arch-vybrid/timer.h
>> create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-pins.h
>> create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-regs.h
>>
[...]
>
>>+
>>+.section ".text.init", "x"
>>+
>>+.globl lowlevel_init
>>+lowlevel_init:
>>+ /* ARM errata ID #468414 */
>>+ mrc 15, 0, r1, c1, c0, 1
>>+ orr r1, r1, #(1 << 5) /* enable L1NEON bit */
>>+ mcr 15, 0, r1, c1, c0, 1
>>+
>
>Does this errata applied to A5 too?
You did not answer this question? :)
[Alison Wang] This errata doesn't apply to A5. I will remove it. Thanks.
>
>>+#ifndef CONFIG_SYS_BOOTHDR
>>+ init_clock
>>+#endif
>>+
>>+ /* r12 saved upper lr*/
>>+ mov pc,lr
>>+
>>+/* Board level setting value */
>>+DDR_PERCHARGE_CMD: .word 0x04008008
>>+DDR_REFRESH_CMD: .word 0x00008010
>>+DDR_LMR1_W: .word 0x00338018
>>+DDR_LMR_CMD: .word 0xB2220000
>>+DDR_TIMING_W: .word 0xB02567A9
>>+DDR_MISC_W: .word 0x000A0104
>>diff --git a/arch/arm/cpu/armv7/vybrid/soc.c
>>b/arch/arm/cpu/armv7/vybrid/soc.c
>>new file mode 100644
>>index 0000000..e73d6c4
>>--- /dev/null
>>+++ b/arch/arm/cpu/armv7/vybrid/soc.c
>>@@ -0,0 +1,42 @@
>>+/*
>>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>>+ *
>>+ * See file CREDITS for list of people who contributed to this
>>+ * project.
>>+ *
>>+ * This program is free software; you can redistribute it and/or
>>+ * modify it under the terms of the GNU General Public License as
>>+ * published by the Free Software Foundation; either version 2 of
>>+ * the License, or (at your option) any later version.
>>+ *
>>+ * This program is distributed in the hope that it will be useful,
>>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>+ * GNU General Public License for more details.
>>+ *
>>+ * You should have received a copy of the GNU General Public License
>>+ * along with this program; if not, write to the Free Software
>>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>>+ * MA 02111-1307 USA
>>+ */
>>+
>>+#include <common.h>
>>+#include <asm/arch/vybrid-regs.h>
>>+#include <asm/arch/clock.h>
>>+#include <asm/arch/sys_proto.h>
>>+
>>+#include <asm/errno.h>
>>+#include <asm/io.h>
>>+
>>+#if !(defined(CONFIG_VYBRID))
>>+#error "CPU_TYPE not defined"
>>+#endif
>>+
>>+u32 get_cpu_rev(void)
>>+{
>>+ int system_rev = 0x600000;
>
>What's the hard code 0x600000 means?
Ditto,
[Alison Wang] Because CPU revision could not read from hardware, I wrote it
like this . I will remove it in the next patch version.
>
>>+ int reg = __raw_readl(ROM_SI_REV);
>>+
>>+ system_rev |= reg;
>>+ return system_rev;
>>+}
[...]
>>+#define _VYBRID_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
>>+ _VYBRID_BUILD_PIN(gp, gi, ga, mi, pi)
>>+
>>+#define _VYBRID_BUILD_NON_GPIO_PIN(mi, pi) \
>>+ _VYBRID_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
>>+
>>+#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
>>+#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
>>+#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) &
>PIN_TO_ALT_GPIO_MASK)
>>+#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
>>+
>>+enum iomux_input_select {
>>+ AUDMUX_P4_INPUT = 0,
>>+};
>
>Could you please consider the common iomux-v3 code?
>[Alison Wang] I consider the common iomux-v3 code, and find that i.mx
>and MVF platform (vybrid) have different registers' definitions for
>IOMUXC. On i.mx there are two registers for mux_mode and control value,
>but on MVF platform there is only one register.
>
>For MVF platform, IOMUXC register is as follows:
>31 30 29 28 27 26 25 24 23 | 22 21 20 | 19 18 17 16
> Reserved | MUX_MODE | Reserved
>15 14 | 13 12 |11 |10 | 9 | 8 7 6 | 5 4 | 3 | 2 | 1 | 0 |
>Reserved | SPEED |SRE|ODE|HYS| DSE | PUS |PKE|PUE|OBE|IBE|
>
>In arch/arm/imx-common/iomux-v3.c,
>u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
>(MUX_PAD_CTRL_MASK is 0x3ffff !)
>
>if (mux_ctrl_ofs)
> __raw_writel(mux_mode, base + mux_ctrl_ofs);
>if (sel_input_ofs)
> __raw_writel(sel_input, base + sel_input_ofs);
>if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
> __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
>
>I think the above codes are not suitable for MVF platform.
>
>In MVF platform, the address for IOMUXC_PTA6 is 4004_8000h base + 0h
>offset, so pad_ctrl_ofs and mux_ctrl_ofs will be 0. I think the codes
>"if (mux_ctrl_ofs)" and " if (!(pad_ctrl & NO_PAD_CTRL) &&
>pad_ctrl_ofs)" are not suitable for MVF platform.
>
>The definitions for some macros such as PAD_CTL_PUS_100K_DOWN are not
>suitable for MVF platform, too.
>
>I think I could use iomux-v3 code, if adding some "#ifdef" for MVF
>platform in iomux-v3 code. But I think it may be better if the code
>could be modified to be suitable for both i.mx and MVF platforms. What's
>your suggestions? Thanks.
>From your comments, the current code is not fit perfectly for the
VF platform, but we can consider changing the code to make it fit for both.
But I do not strongly insist that we must use the same code. If you find it's
Ugly to support both with the same code, I'm fine with the current code.
[Alison Wang] I will change the code to make it fit for both in the next patch
version. Thanks.
>
>Jason Liu
>>+
>>+#endif /* __ASSEMBLY__ */
>>+#endif /* __ASM_ARCH_VYBRID_PINS_H__ */
>>diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-regs.h
>>b/arch/arm/include/asm/arch-vybrid/vybrid-regs.h
>>new file mode 100644
>>index 0000000..51cfba5
>
>[..]
>
>Thanks!
>
>Best Regards,
>Alison Wang
>
>
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