Dear Akshay Saraswat,
On 22/03/13 21:26, Akshay Saraswat wrote:
> According to the latest exynos5 user manual, the equation for
> calculating PLL output was changed to
> FOUT= MDIV x FIN/(PDIV x 2^SDIV)
> earlier it was
> FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
> So updating the clock code accordingly.
>
> Signed-off-by: Hatim Ali <hatim...@samsung.com>
> Signed-off-by: Akshay Saraswat <aksha...@samsung.com>
> ---
> arch/arm/cpu/armv7/exynos/clock.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index 956427c..5299bc7 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -73,10 +73,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r,
> unsigned int k)
> /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
> fout = (m + k / 1024) * (freq / (p * (1 << s)));
> } else {
> - if (s < 1)
> - s = 1;
> - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
> - fout = m * (freq / (p * (1 << (s - 1))));
> + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
> + fout = m * (freq / (p * (1 << s)));
> }
>
> return fout;
>
applied to u-boot-samsung.
Thanks,
Minkyu Kang.
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