Hi, Stefano, Fabio, On Thu, Jun 6, 2013 at 6:39 AM, Fabio Estevam <feste...@gmail.com> wrote: > On Thu, Jun 6, 2013 at 10:34 AM, Stefano Babic <sba...@denx.de> wrote: >> Could be the same as the issue reported by Fabio at >> http://patchwork.ozlabs.org/patch/246928/ ? > > Yes, please apply this one and also: > http://patchwork.ozlabs.org/patch/248877/ > > With both patches applied SD functionality works well on mx6qsabresd.
Will do. Also, I was looking around and came across this VSELECT bit in the VEND_SPEC register (219_80C0 Vendor Specific Register (uSDHC3_VEND_SPEC) ) It is used to generate low voltage, like 1.8V (n bus SD3 here) which I think is needed for DDR mode? The Freescale code is using it here: /* Switch voltage to 1.8V if CMD11 succeeded */ if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { /* Set SD_VSELECT to switch to 1.8V */ u32 reg; reg = readl(®s->vendorspec); reg |= VENDORSPEC_VSELECT; writel(reg, ®s->vendorspec); /* Sleep for 5 ms - max time for card to switch to 1.8V */ udelay(5000); /* Turn on SD clock */ writel(reg | VENDORSPEC_FRC_SDCLK_ON, ®s->vendorspec); while (!(readl(®s->prsstat) & PRSSTAT_DAT0)) ; /* restore SD clock status */ writel(reg, ®s->vendorspec); } "drivers/mmc/imx_esdhc.c" 714 lines --31%-- -jfs _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot