Synchronize the code with mips64/cache.S, in order to allow further unifications.
Signed-off-by: Gabor Juhos <juh...@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierz...@googlemail.com> --- arch/mips/cpu/mips32/cache.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 8158ea8..6d31909 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -34,7 +34,7 @@ #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT #endif -#define RA t8 +#define RA t9 /* * 16kB is the maximum size of instruction and data caches on MIPS 4K, -- 1.7.10 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
