On Thu, Jun 20, 2013 at 8:26 AM, SARTRE Leo <lsar...@adeneo-embedded.com> wrote: > cgtqmx6eval.c: add Micrel KSZ9031 Ethernet transceiver > README : U-boot works both on SPI-NOR and SDcard > > Signed-off-by: Leo Sartre <lsar...@adeneo-embedded.com> > --- > board/congatec/cgtqmx6eval/README | 3 +- > board/congatec/cgtqmx6eval/cgtqmx6eval.c | 112 > ++++++++++++++++++++++++++++++ > include/configs/cgtqmx6eval.h | 13 ++++ > 3 files changed, 126 insertions(+), 2 deletions(-) > > diff --git a/board/congatec/cgtqmx6eval/README > b/board/congatec/cgtqmx6eval/README > index bbf0f75..5e76d2a 100644 > --- a/board/congatec/cgtqmx6eval/README > +++ b/board/congatec/cgtqmx6eval/README > @@ -7,8 +7,7 @@ Conga-QEVAl Evaluation Carrier board with qmx6 quad module. > 1. Boot source, boot from SD card > --------------------------------- > > -This version of u-boot works only on the SD card. By default, the > -Congatec board can boot only from the SPI-NOR. > +By default, the Congatec board can boot only from the SPI-NOR. > But, with the u-boot version provided with the board you can write boot > registers to force the board to reboot and boot from the SD slot. If > "bmode" command is not available from your pre-installed u-boot, these
Please change this in another patch. This one you can add Stefano in Cc so he can apply it in his tree. > diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c > b/board/congatec/cgtqmx6eval/cgtqmx6eval.c > index f70f674..00088fb 100644 > --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c > +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c > @@ -30,6 +30,8 @@ > #include <asm/imx-common/iomux-v3.h> > #include <asm/imx-common/boot_mode.h> > #include <mmc.h> > +#include <micrel.h> > +#include <miiphy.h> > #include <fsl_esdhc.h> > > DECLARE_GLOBAL_DATA_PTR; > @@ -40,6 +42,9 @@ DECLARE_GLOBAL_DATA_PTR; > #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ > PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) > > +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ > + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) > + > int dram_init(void) > { > gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); > @@ -76,6 +81,113 @@ iomux_v3_cfg_t const usdhc4_pads[] = { > MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ > }; > > +iomux_v3_cfg_t const enet_pads1[] = { > + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), > + /* pin 35 - 1 (PHY_AD2) on reset */ > + MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* pin 32 - 1 - (MODE0) all */ > + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* pin 31 - 1 - (MODE1) all */ > + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* pin 28 - 1 - (MODE2) all */ > + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* pin 27 - 1 - (MODE3) all */ > + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ > + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* pin 42 PHY nRST */ > + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +iomux_v3_cfg_t const enet_pads2[] = { > + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), > +}; > + > +static void setup_iomux_enet(void) > +{ > + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); > + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); > + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); > + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); > + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); > + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); > + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); > + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); > + > + /* Need delay 10ms according to KSZ9031 spec */ > + udelay(1000 * 10); > + gpio_set_value(IMX_GPIO_NR(3, 23), 1); > + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); > +} > + > +int board_phy_config(struct phy_device *phydev) > +{ > + ksz9031_phy_extended_write(phydev, 2, > + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, > + 0x0000); > + ksz9031_phy_extended_write(phydev, 2, > + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, > + 0x0000); > + ksz9031_phy_extended_write(phydev, 2, > + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, > + 0xFFFF); > + ksz9031_phy_extended_write(phydev, 2, > + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, > + 0x3FFF); > + > + phydev->drv->config(phydev); > + > + return 0; > +} > + > +int board_eth_init(bd_t *bis) > +{ > + uint32_t base = IMX_FEC_BASE; > + struct mii_dev *bus = NULL; > + struct phy_device *phydev = NULL; > + int ret; > + > + setup_iomux_enet(); > + > +#ifdef CONFIG_FEC_MXC Shouldn't this cover the whole function? > + bus = fec_get_miibus(base, -1); > + if (!bus) > + return 0; > + /* scan phy 6*/ > + phydev = phy_find_by_mask(bus, (0xf << 6), PHY_INTERFACE_MODE_RGMII); > + > + if (!phydev) { > + free(bus); > + printf("No phy found\n"); > + return 0; > + } > + printf("using phy at %d\n", phydev->addr); > + ret = fec_probe(bis, -1, base, bus, phydev); > + if (ret) { > + printf("FEC MXC: %s:failed\n", __func__); > + free(phydev); > + free(bus); > + } > +#endif > + return 0; > +} -- Otavio Salvador O.S. Systems http://www.ossystems.com.br http://projetos.ossystems.com.br Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot