On Thu, Jun 27, 2013 at 4:50 AM, Zhang Haijun-B42677 <b42...@freescale.com>wrote:
> Hi, Fleming and Fabio > > Sorry to reply to you so late. > > As our manual described. > > In the eSDHC, the data buffer can hold up to 128 words (32-bit). > > The watermark levels for both write and read can be configured for CPU > polling mode. > The watermark level can be from 1 word to the maximum of 128 words. > > For both DMA read and write, the burst length, can be configured from 1 to > the maximum of 16. > > The host driver may configure watermark level and burst length value > according to the system > situation and requirement in the watermark level register (WML). > I think you may have misunderstood the WML register. My read of the manual indicates it is most definitely necessary for DMA. I think it is also necessary for polling mode, and WML configuration was not added properly when polling mode support was added to the driver. The solution may be to set up WML for both modes, but the manual is a bit unclear (it sometimes likes to refer to polling mode as "External DMA"). Andy
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