hi Albert, On Mon Jul 08, 2013 at 09:55:51PM +0200, Albert ARIBAUD wrote:
<snip> > > > Invalidating the cache in addition to flushing it would not prevent > > > further writes from dirtying the cache lines if they happen before > > > the cache is disabled. > > > > I have a doubt on this. The arm926ejs uses a read-allocate policy, > > wherein a new cache line is allocated only on a read miss -- a write > > to an address not present in the cache gets written to memory. So if > > the cache line is invalidated, how will data get written to the cache. > > The arm926ej-s data cache does not have a single fixed policy, and > does not have a bypass-on-write policy, only write-through and > copy-back. > > Other, more complex, policies may be defined, but at the MMU, not cache, > level, and those are not constant for all arm926ej-s based SoCs; not > even constant for a given SoC as they are configurable at run-time to > fit the chosen system addressing map. Can you please elucidate on these policies. Based on my reading of the arm developers manual and the arm926ejs trm, the mmu makes a particular region cacheable and/or write bufferable. I did not find mention of any other policies. Maybe pointers or links to the documents would help. > (Besides, bypassing the cache for writes and not reads is of little > interest for plain DDR caching.) Again, afaik this is independent of the target interface that is being cached(if i've missed something, can you please point me to the document). Thanks. -sughosh _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot