From: Fabio Estevam <fabio.este...@freescale.com>
Currently we have the following behavior in ehci_hcd_init()
- Read csmr1 register, clear bit 26 and then set bit 26.
However a little bit later we call set_usb_phy_clk() which clears bit 26, so
let's get rid of the unnecessary code.
Signed-off-by: Fabio Estevam <fabio.este...@freescale.com>
---
drivers/usb/host/ehci-mx5.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index f43c38d..6178a1d 100644
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -229,15 +229,6 @@ void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci,
int port)
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
-#ifdef CONFIG_MX53
- struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR;
- u32 reg;
-
- reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26);
- /* derive USB PHY clock multiplexer from PLL3 */
- reg |= 1 << 26;
- __raw_writel(reg, &sc_regs->cscmr1);
-#endif
set_usboh3_clk();
enable_usboh3_clk(1);
--
1.8.1.2
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