Hello Lokesh, tom,
Am 30.07.2013 09:13, schrieb Heiko Schocher:
Hello Lokesh,
Am 30.07.2013 07:39, schrieb Lokesh Vutla:
Hi Heiko,
On Tuesday 30 July 2013 10:39 AM, Heiko Schocher wrote:
add support for the am335x based boards from siemens:
[...]
- [U-Boot] net, phy, cpsw: fix gigabit register access
http://patchwork.ozlabs.org/patch/261087/
I have just posted a V2 of AM33xx cleanup series, Can you rebase on top of that.
There was a bug in my series. Multiplier for DDR DPLL was hard coded for all
the boards.
IN V2, the common file expects a function which returns ddr_dpll_parms.
So can you add the following code in your board files:
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
<DXR2_PLL_FREQ>, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params *get_dpll_ddr_params(void)
{
return&dpll_ddr;
}
The M value we pass in config_ddr is not used(should be cleaned up)
Please let me know if I am not clear.
Sorry for the noise...
No problem, thanks for the info... Hmm.. just rebased against
top of u-boot-ti and your patches, but ethernet is not longer
working :-( I get:
U-Boot# ping 192.168.1.1
link up on port 0, speed 1000, full duplex
data abort
MAYBE you should read doc/README.arm-unaligned-accesses
pc : [<9ff6ed7c>] lr : [<9ff6f810>]
sp : 9ef40d50 ip : 0019010c fp : 00000000
r10: 33221100 r9 : 0000002e r8 : 9ef40f38
r7 : 9ffed56c r6 : 9ef45db0 r5 : 00000004 r4 : 9ef45d50
r3 : 000005ee r2 : 9ffee2c0 r1 : 9ef45db0 r0 : 9ef45d50
Flags: nzCv IRQs off FIQs on Mode SVC_32
Resetting CPU ...
resetting ...
U-Boot SPL 2013.07-00098-g2b19a9e (Jul 30 2013 - 09:00:03)
Digging in this ...
Fixed. reason was commit 2bf36ac638ab2db9f0295aa47064976eeebf80c1
which introduced bd_ram_ofs field to struct cpsw_platform_data
I rebased my patches on Lokeshs patches and repost my series on
top of it.
bye,
Heiko
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