This patch adds a driver for Renesas SoC's Queued SPI bus.
This supports with 8 bits per transfer to use with SPI flash.
Signed-off-by: Kouei Abe <kouei.abe...@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu...@renesas.com>
---
drivers/spi/Makefile | 1 +
drivers/spi/sh_qspi.c | 204 ++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/spi/sh_qspi.h | 56 ++++++++++++++
3 files changed, 261 insertions(+)
create mode 100644 drivers/spi/sh_qspi.c
create mode 100644 drivers/spi/sh_qspi.h
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 019132e..f71c089 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
+COBJS-$(CONFIG_SH_QSPI) += sh_qspi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
new file mode 100644
index 0000000..82bb49f
--- /dev/null
+++ b/drivers/spi/sh_qspi.c
@@ -0,0 +1,204 @@
+/*
+ * drivers/spi/sh_qspi.c
+ * SH QSPI driver
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu...@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include "sh_qspi.h"
+
+static void sh_qspi_writeb(unsigned char data, unsigned char *reg)
+{
+ writeb(data, reg);
+}
+
+static void sh_qspi_writew(unsigned short data, unsigned short *reg)
+{
+ writew(data, reg);
+}
+
+static void sh_qspi_writel(unsigned long data, unsigned long *reg)
+{
+ writel(data, reg);
+}
+
+static unsigned char sh_qspi_readb(unsigned char *reg)
+{
+ return readb(reg);
+}
+
+static unsigned short sh_qspi_readw(unsigned short *reg)
+{
+ return readw(reg);
+}
+
+void spi_init(void)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct sh_qspi *ss;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ ss = spi_alloc_slave(struct sh_qspi, bus, cs);
+ if (!ss)
+ return NULL;
+
+ ss->regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE;
+
+ /* QSPI initialize */
+ sh_qspi_writeb(0x08, &ss->regs->spcr);
+ sh_qspi_writeb(0x00, &ss->regs->sslp);
+ sh_qspi_writeb(0x06, &ss->regs->sppcr);
+ sh_qspi_writeb(0x01, &ss->regs->spbr);
+ sh_qspi_writeb(0x00, &ss->regs->spdcr);
+ sh_qspi_writeb(0x00, &ss->regs->spckd);
+ sh_qspi_writeb(0x00, &ss->regs->sslnd);
+ sh_qspi_writeb(0x00, &ss->regs->spnd);
+ sh_qspi_writew(0xe084, &ss->regs->spcmd0);
+ sh_qspi_writew(0x8084, &ss->regs->spcmd0);
+ sh_qspi_writeb(0xc0, &ss->regs->spbfcr);
+ sh_qspi_writeb(0x00, &ss->regs->spbfcr);
+ sh_qspi_writeb(0x00, &ss->regs->spscr);
+ sh_qspi_writeb(0x48, &ss->regs->spcr);
+
+ return &ss->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct sh_qspi *spi = to_sh_qspi(slave);
+
+ free(spi);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+static int sh_qspi_xfer(struct sh_qspi *ss, unsigned char *tdata,
+ unsigned char *rdata, unsigned long flags)
+{
+ while (!(sh_qspi_readb(&ss->regs->spsr) & SH_QSPI_SPTEF)) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+
+ sh_qspi_writeb(*tdata, (unsigned char *)(&ss->regs->spdr));
+
+ while ((sh_qspi_readw(&ss->regs->spbdcr) != 0x01)) {
+ int i = 100;
+
+ if (ctrlc())
+ return 1;
+ while (i--)
+ ;
+ }
+
+ while (!(sh_qspi_readb(&ss->regs->spsr) & SH_QSPI_SPRFF)) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+
+ *rdata = sh_qspi_readb((unsigned char *)(&ss->regs->spdr));
+
+ return 0;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct sh_qspi *ss = to_sh_qspi(slave);
+ unsigned int nbyte;
+ int ret = 0;
+ unsigned char *tdata, *rdata, dtdata = 0, drdata;
+
+ if (dout == NULL && din == NULL) {
+ if (flags & SPI_XFER_END)
+ sh_qspi_writeb(0x08, &ss->regs->spcr);
+ return 0;
+ }
+
+ if (bitlen % 8) {
+ printf("spi_xfer: bitlen is not 8bit alined %d", bitlen);
+ return 1;
+ }
+
+ nbyte = bitlen / 8;
+
+ if (flags & SPI_XFER_BEGIN) {
+ sh_qspi_writeb(0x08, &ss->regs->spcr);
+
+ sh_qspi_writew(0xe084, &ss->regs->spcmd0);
+
+ if (flags & SPI_XFER_END)
+ sh_qspi_writel(nbyte, &ss->regs->spbmul0);
+ else
+ sh_qspi_writel(0x100000, &ss->regs->spbmul0);
+
+ sh_qspi_writeb(0xc0, &ss->regs->spbfcr);
+ sh_qspi_writeb(0x00, &ss->regs->spbfcr);
+ sh_qspi_writeb(0x00, &ss->regs->spscr);
+ sh_qspi_writeb(0x48, &ss->regs->spcr);
+ }
+
+ if (dout != NULL)
+ tdata = (unsigned char *)dout;
+ else
+ tdata = &dtdata;
+
+ if (din != NULL)
+ rdata = din;
+ else
+ rdata = &drdata;
+
+ while (nbyte > 0) {
+ ret = sh_qspi_xfer(ss, tdata, rdata, flags);
+ if (ret)
+ break;
+
+ if (dout != NULL)
+ tdata++;
+
+ if (din != NULL)
+ rdata++;
+
+ nbyte--;
+ }
+
+ if (flags & SPI_XFER_END)
+ sh_qspi_writeb(0x08, &ss->regs->spcr);
+
+ return ret;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+}
diff --git a/drivers/spi/sh_qspi.h b/drivers/spi/sh_qspi.h
new file mode 100644
index 0000000..9898259
--- /dev/null
+++ b/drivers/spi/sh_qspi.h
@@ -0,0 +1,56 @@
+/*
+ * drivers/spi/sh_qspi.h
+ * SH QSPI driver definition
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SH_QSPI_H__
+#define __SH_QSPI_H__
+
+#include <spi.h>
+
+struct sh_qspi_regs {
+ unsigned char spcr;
+ unsigned char sslp;
+ unsigned char sppcr;
+ unsigned char spsr;
+ unsigned long spdr;
+ unsigned char spscr;
+ unsigned char spssr;
+ unsigned char spbr;
+ unsigned char spdcr;
+ unsigned char spckd;
+ unsigned char sslnd;
+ unsigned char spnd;
+ unsigned char dummy0;
+ unsigned short spcmd0;
+ unsigned short spcmd1;
+ unsigned short spcmd2;
+ unsigned short spcmd3;
+ unsigned char spbfcr;
+ unsigned char dummy1;
+ unsigned short spbdcr;
+ unsigned long spbmul0;
+ unsigned long spbmul1;
+ unsigned long spbmul2;
+ unsigned long spbmul3;
+};
+
+/* SPSR */
+#define SH_QSPI_SPRFF 0x80
+#define SH_QSPI_SPTEF 0x20
+
+struct sh_qspi {
+ struct spi_slave slave;
+ struct sh_qspi_regs *regs;
+};
+
+static inline struct sh_qspi *to_sh_qspi(struct spi_slave *slave)
+{
+ return container_of(slave, struct sh_qspi, slave);
+}
+
+#endif
--
1.8.3.2
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