On Monday 06 April 2009 04:27:10 Wolfgang Denk wrote: > In message Mike Frysinger wrote: > > From: Graf Yang <graf.y...@analog.com> > > > > We need to make sure the data written to the nand flash controller makes > > it there before we start polling its status register. Otherwise, we may > > get stale data and return before the controller is actually ready. > > > > Signed-off-by: Graf Yang <graf.y...@analog.com> > > Signed-off-by: Mike Frysinger <vap...@gentoo.org> > > --- > > drivers/mtd/nand/bfin_nand.c | 1 + > > 1 files changed, 1 insertions(+), 0 deletions(-) > > > > diff --git a/drivers/mtd/nand/bfin_nand.c b/drivers/mtd/nand/bfin_nand.c > > index f6a0835..f134ef1 100644 > > --- a/drivers/mtd/nand/bfin_nand.c > > +++ b/drivers/mtd/nand/bfin_nand.c > > @@ -98,6 +98,7 @@ static void bfin_nfc_read_buf(struct mtd_info *mtd, > > uint8_t *buf, int len) > > > > /* Contents do not matter */ > > bfin_write_NFC_DATA_RD(0x0000); > > + SSYNC(); > > Should such syncing not be integral part of the > bfin_write_NFC_DATA_RD() aceessor?
on the Blackfin processor, the ssync instruction is a barrier rather than a hard requirement (well, that isnt 100% true, but those edge cases dont apply to peripherals). since the NFC_DATA_RD MMR could be written in such a way to not need the barrier, we dont place ssync's into the MMR defines. especially because the ssync instruction flushes all buffers in the chip, not just the peripherals, so it can be pretty heavy handed. -mike
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