Chris, Thanks for the debugging work. As I suspected, it's related to I2C change. It's probably a problem in the board header file. If you fix it, please submit a patch. Otherwise, I will look into it tomorrow.
York -------- Original Message -------- From: Chris Packham Sent: Mon, 09/09/2013 22:49 To: sun york-R58495 CC: u-boot ; Xie Shaohui-B21989 ; h...@denx.de Subject: Re: P2041RDB fails to boot with master (and 2013.10-rc1) git bisect points to the following commit 00f792e0df9ae942427e44595a0f4379582accee is the first bad commit commit 00f792e0df9ae942427e44595a0f4379582accee Author: Heiko Schocher <h...@denx.de> Date: Wed Oct 24 13:48:22 2012 +0200 i2c, fsl_i2c: switch to new multibus/multiadapter support - added to fsl_i2c driver new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Heiko Schocher <h...@denx.de> Cc: Simon Glass <s...@chromium.org> Cc: Stephen Warren <swar...@wwwdotorg.org> On Tue, Sep 10, 2013 at 5:31 PM, sun york-R58495 <r58...@freescale.com> wrote: > Chris, > > Thanks a lot to bring this to our attention. > > A brief look at the log shows the SPD wasn't found, probably due to recent > I2C change. We will address this issue as soon as possible. > > York > > > > -------- Original Message -------- > From: Chris Packham > Sent: Mon, 09/09/2013 22:26 > To: u-boot > CC: sun york-R58495 ; Xie Shaohui-B21989 ; aflem...@freescale.com > Subject: P2041RDB fails to boot with master (and 2013.10-rc1) > > Hi, > > I was just looking at something else and found that my P2041RDB no > longer boots from the master branch of u-boot.git (it hangs after DDR > initialisation). I checked 2013.10-rc1, same problem. 2013.07 works. > > I haven't bisected further than that. I just thought I'd fire this off > now since it appears to be a regression that might affect 2013.10. > > Thanks, > Chris > > -- > > Output from 2013.10-rc1 > > U-Boot 2013.10-rc1 (Sep 10 2013 - 17:08:26) > > CPU0: P2041E, Version: 1.0, (0x82180110) > Core: e500mc, Version: 2.2, (0x80230022) > Clock Configuration: > CPU0:1500 MHz, CPU1:1500 MHz, CPU2:1500 MHz, CPU3:1500 MHz, > CCB:750 MHz, > DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:93.750 > MHz > FMAN1: 583.333 MHz > QMAN: 375 MHz > PME: 375 MHz > L1: D-cache 32 kB enabled > I-cache 32 kB enabled > Reset Configuration Word (RCW): > 00000000: 12600000 00000000 241c0000 00000000 > 00000010: 249f40c0 c3c02000 fe800000 40000000 > 00000020: 00000000 00000000 00000000 d0030f07 > 00000030: 00000000 00000000 00000000 00000000 > Board: P2041RDB, CPLD version: 3.0 vBank: 0 > SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz > I2C: ready > SPI: ready > DRAM: Initializing....WARNING: Calling __hwconfig without a buffer > and before environment is ready > using SPD > DDR: failed to read SPD from address 82 > WARNING: Calling __hwconfig without a buffer and before environment is ready > WARNING: Calling __hwconfig without a buffer and before environment is ready > 16 MiB (DDR2, 64-bit, CL=0.5, ECC off) > Testing 0x00000000 - 0x00ffffff > Remap DDR > > Output from 2013.07 > > > U-Boot 2013.07 (Sep 10 2013 - 17:00:18) > > CPU0: P2041E, Version: 1.0, (0x82180110) > Core: e500mc, Version: 2.2, (0x80230022) > Clock Configuration: > CPU0:1500 MHz, CPU1:1500 MHz, CPU2:1500 MHz, CPU3:1500 MHz, > CCB:750 MHz, > DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:93.750 > MHz > FMAN1: 583.333 MHz > QMAN: 375 MHz > PME: 375 MHz > L1: D-cache 32 kB enabled > I-cache 32 kB enabled > Board: P2041RDB, CPLD version: 3.0 vBank: 0 > Reset Configuration Word (RCW): > 00000000: 12600000 00000000 241c0000 00000000 > 00000010: 249f40c0 c3c02000 fe800000 40000000 > 00000020: 00000000 00000000 00000000 d0030f07 > 00000030: 00000000 00000000 00000000 00000000 > SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz > I2C: ready > SPI: ready > DRAM: Initializing....using SPD > Detected UDIMM UG51U6400N8SU-ACF > 2 GiB left unmapped > 4 GiB (DDR3, 64-bit, CL=9, ECC off) > DDR Chip-Select Interleaving Mode: CS0+CS1 > Testing 0x00000000 - 0x7fffffff > Testing 0x80000000 - 0xffffffff > Remap DDR 2 GiB left unmapped > > POST memory PASSED > Flash: 128 MiB > L2: 128 KB enabled > Corenet Platform Cache: 1024 KB enabled > SERDES: bank 3 disabled > SRIO1: disabled > SRIO2: disabled > NAND: 0 MiB > MMC: FSL_SDHC: 0 > EEPROM: Invalid ID (ff ff ff ff) > PCIe1: disabled > PCIe2: Root Complex, no link, regs @ 0xfe201000 > PCIe2: Bus 00 - 00 > PCIe3: disabled > In: serial > Out: serial > Err: serial > Net: Initializing Fman > Fman1: DTSEC3 set to unknown interface 12 > Fman1: Uploading microcode version 101.8.0 > Phy not found > PHY reset timed out > FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC4, FM1@DTSEC5, FM1@TGEC1 > => >
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