Hi Masahiro, And this driver works fine when my patch (http://patchwork.ozlabs.org/patch/276429/) applied.
Best Regards, Sergey Kostanbaev On Tue, Sep 24, 2013 at 5:32 AM, Masahiro Yamada <yamad...@jp.panasonic.com> wrote: > commit 716f7ade104a9aeed647e19a8b8c9ed9f491359d > deleted all ep93xx SoC boards. > > Now there are no boards enabling CONFIG_EP93XX, > no boards using ep93xx_eth driver. > > Signed-off-by: Masahiro Yamada <yamad...@jp.panasonic.com> > --- > doc/driver-model/UDM-net.txt | 6 - > drivers/net/Makefile | 1 - > drivers/net/ep93xx_eth.c | 639 > ------------------------------------------- > drivers/net/ep93xx_eth.h | 127 --------- > include/common.h | 3 +- > include/netdev.h | 1 - > 6 files changed, 1 insertion(+), 776 deletions(-) > delete mode 100644 drivers/net/ep93xx_eth.c > delete mode 100644 drivers/net/ep93xx_eth.h > > diff --git a/doc/driver-model/UDM-net.txt b/doc/driver-model/UDM-net.txt > index 097ed69..f447f59 100644 > --- a/doc/driver-model/UDM-net.txt > +++ b/doc/driver-model/UDM-net.txt > @@ -217,12 +217,6 @@ III) Analysis of in-tree drivers > This driver uses the standard new networking API, therefore there should > be no > obstacles throughout the conversion process. > > - drivers/net/ep93xx_eth.c > - ------------------------ > - > - This driver uses the standard new networking API, therefore there should > be no > - obstacles throughout the conversion process. > - > drivers/net/ethoc.c > ------------------- > > diff --git a/drivers/net/Makefile b/drivers/net/Makefile > index 18fd54f..7436e64 100644 > --- a/drivers/net/Makefile > +++ b/drivers/net/Makefile > @@ -25,7 +25,6 @@ COBJS-$(CONFIG_E1000) += e1000.o > COBJS-$(CONFIG_E1000_SPI) += e1000_spi.o > COBJS-$(CONFIG_EEPRO100) += eepro100.o > COBJS-$(CONFIG_ENC28J60) += enc28j60.o > -COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o > COBJS-$(CONFIG_ETHOC) += ethoc.o > COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o > COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o > diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c > deleted file mode 100644 > index 1c09f10..0000000 > --- a/drivers/net/ep93xx_eth.c > +++ /dev/null > @@ -1,639 +0,0 @@ > -/* > - * Cirrus Logic EP93xx ethernet MAC / MII driver. > - * > - * Copyright (C) 2010, 2009 > - * Matthias Kaehlcke <matth...@kaehlcke.net> > - * > - * Copyright (C) 2004, 2005 > - * Cory T. Tusar, Videon Central, Inc., <ctu...@videon-central.com> > - * > - * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver, > - * which is > - * > - * (C) Copyright 2002 2003 > - * Adam Bezanson, Network Audio Technologies, Inc. > - * <bezan...@netaudiotech.com> > - * > - * SPDX-License-Identifier: GPL-2.0+ > - */ > - > -#include <command.h> > -#include <common.h> > -#include <asm/arch/ep93xx.h> > -#include <asm/io.h> > -#include <malloc.h> > -#include <miiphy.h> > -#include <linux/types.h> > -#include "ep93xx_eth.h" > - > -#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv) > -#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs) > - > -/* ep93xx_miiphy ops forward declarations */ > -static int ep93xx_miiphy_read(const char * const dev, unsigned char const > addr, > - unsigned char const reg, unsigned short * const > value); > -static int ep93xx_miiphy_write(const char * const dev, unsigned char const > addr, > - unsigned char const reg, unsigned short const value); > - > -#if defined(EP93XX_MAC_DEBUG) > -/** > - * Dump ep93xx_mac values to the terminal. > - */ > -static void dump_dev(struct eth_device *dev) > -{ > - struct ep93xx_priv *priv = GET_PRIV(dev); > - int i; > - > - printf("\ndump_dev()\n"); > - printf(" rx_dq.base %p\n", priv->rx_dq.base); > - printf(" rx_dq.current %p\n", priv->rx_dq.current); > - printf(" rx_dq.end %p\n", priv->rx_dq.end); > - printf(" rx_sq.base %p\n", priv->rx_sq.base); > - printf(" rx_sq.current %p\n", priv->rx_sq.current); > - printf(" rx_sq.end %p\n", priv->rx_sq.end); > - > - for (i = 0; i < NUMRXDESC; i++) > - printf(" rx_buffer[%2.d] %p\n", i, NetRxPackets[i]); > - > - printf(" tx_dq.base %p\n", priv->tx_dq.base); > - printf(" tx_dq.current %p\n", priv->tx_dq.current); > - printf(" tx_dq.end %p\n", priv->tx_dq.end); > - printf(" tx_sq.base %p\n", priv->tx_sq.base); > - printf(" tx_sq.current %p\n", priv->tx_sq.current); > - printf(" tx_sq.end %p\n", priv->tx_sq.end); > -} > - > -/** > - * Dump all RX status queue entries to the terminal. > - */ > -static void dump_rx_status_queue(struct eth_device *dev) > -{ > - struct ep93xx_priv *priv = GET_PRIV(dev); > - int i; > - > - printf("\ndump_rx_status_queue()\n"); > - printf(" descriptor address word1 word2\n"); > - for (i = 0; i < NUMRXDESC; i++) { > - printf(" [ %p ] %08X %08X\n", > - priv->rx_sq.base + i, > - (priv->rx_sq.base + i)->word1, > - (priv->rx_sq.base + i)->word2); > - } > -} > - > -/** > - * Dump all RX descriptor queue entries to the terminal. > - */ > -static void dump_rx_descriptor_queue(struct eth_device *dev) > -{ > - struct ep93xx_priv *priv = GET_PRIV(dev); > - int i; > - > - printf("\ndump_rx_descriptor_queue()\n"); > - printf(" descriptor address word1 word2\n"); > - for (i = 0; i < NUMRXDESC; i++) { > - printf(" [ %p ] %08X %08X\n", > - priv->rx_dq.base + i, > - (priv->rx_dq.base + i)->word1, > - (priv->rx_dq.base + i)->word2); > - } > -} > - > -/** > - * Dump all TX descriptor queue entries to the terminal. > - */ > -static void dump_tx_descriptor_queue(struct eth_device *dev) > -{ > - struct ep93xx_priv *priv = GET_PRIV(dev); > - int i; > - > - printf("\ndump_tx_descriptor_queue()\n"); > - printf(" descriptor address word1 word2\n"); > - for (i = 0; i < NUMTXDESC; i++) { > - printf(" [ %p ] %08X %08X\n", > - priv->tx_dq.base + i, > - (priv->tx_dq.base + i)->word1, > - (priv->tx_dq.base + i)->word2); > - } > -} > - > -/** > - * Dump all TX status queue entries to the terminal. > - */ > -static void dump_tx_status_queue(struct eth_device *dev) > -{ > - struct ep93xx_priv *priv = GET_PRIV(dev); > - int i; > - > - printf("\ndump_tx_status_queue()\n"); > - printf(" descriptor address word1\n"); > - for (i = 0; i < NUMTXDESC; i++) { > - printf(" [ %p ] %08X\n", > - priv->rx_sq.base + i, > - (priv->rx_sq.base + i)->word1); > - } > -} > -#else > -#define dump_dev(x) > -#define dump_rx_descriptor_queue(x) > -#define dump_rx_status_queue(x) > -#define dump_tx_descriptor_queue(x) > -#define dump_tx_status_queue(x) > -#endif /* defined(EP93XX_MAC_DEBUG) */ > - > -/** > - * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until > - * it's cleared. > - */ > -static void ep93xx_mac_reset(struct eth_device *dev) > -{ > - struct mac_regs *mac = GET_REGS(dev); > - uint32_t value; > - > - debug("+ep93xx_mac_reset"); > - > - value = readl(&mac->selfctl); > - value |= SELFCTL_RESET; > - writel(value, &mac->selfctl); > - > - while (readl(&mac->selfctl) & SELFCTL_RESET) > - ; /* noop */ > - > - debug("-ep93xx_mac_reset"); > -} > - > -/* Eth device open */ > -static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd) > -{ > - struct ep93xx_priv *priv = GET_PRIV(dev); > - struct mac_regs *mac = GET_REGS(dev); > - uchar *mac_addr = dev->enetaddr; > - int i; > - > - debug("+ep93xx_eth_open"); > - > - /* Reset the MAC */ > - ep93xx_mac_reset(dev); > - > - /* Reset the descriptor queues' current and end address values */ > - priv->tx_dq.current = priv->tx_dq.base; > - priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC); > - > - priv->tx_sq.current = priv->tx_sq.base; > - priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC); > - > - priv->rx_dq.current = priv->rx_dq.base; > - priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC); > - > - priv->rx_sq.current = priv->rx_sq.base; > - priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC); > - > - /* > - * Set the transmit descriptor and status queues' base address, > - * current address, and length registers. Set the maximum frame > - * length and threshold. Enable the transmit descriptor processor. > - */ > - writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd); > - writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd); > - writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen); > - > - writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd); > - writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd); > - writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen); > - > - writel(0x00040000, &mac->txdthrshld); > - writel(0x00040000, &mac->txststhrshld); > - > - writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen); > - writel(BMCTL_TXEN, &mac->bmctl); > - > - /* > - * Set the receive descriptor and status queues' base address, > - * current address, and length registers. Enable the receive > - * descriptor processor. > - */ > - writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd); > - writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd); > - writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen); > - > - writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd); > - writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd); > - writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen); > - > - writel(0x00040000, &mac->rxdthrshld); > - > - writel(BMCTL_RXEN, &mac->bmctl); > - > - writel(0x00040000, &mac->rxststhrshld); > - > - /* Wait until the receive descriptor processor is active */ > - while (!(readl(&mac->bmsts) & BMSTS_RXACT)) > - ; /* noop */ > - > - /* > - * Initialize the RX descriptor queue. Clear the TX descriptor queue. > - * Clear the RX and TX status queues. Enqueue the RX descriptor and > - * status entries to the MAC. > - */ > - for (i = 0; i < NUMRXDESC; i++) { > - /* set buffer address */ > - (priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i]; > - > - /* set buffer length, clear buffer index and NSOF */ > - (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN; > - } > - > - memset(priv->tx_dq.base, 0, > - (sizeof(struct tx_descriptor) * NUMTXDESC)); > - memset(priv->rx_sq.base, 0, > - (sizeof(struct rx_status) * NUMRXDESC)); > - memset(priv->tx_sq.base, 0, > - (sizeof(struct tx_status) * NUMTXDESC)); > - > - writel(NUMRXDESC, &mac->rxdqenq); > - writel(NUMRXDESC, &mac->rxstsqenq); > - > - /* Set the primary MAC address */ > - writel(AFP_IAPRIMARY, &mac->afp); > - writel(mac_addr[0] | (mac_addr[1] << 8) | > - (mac_addr[2] << 16) | (mac_addr[3] << 24), > - &mac->indad); > - writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper); > - > - /* Turn on RX and TX */ > - writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON | > - RXCTL_RCRCA | RXCTL_MA, &mac->rxctl); > - writel(TXCTL_STXON, &mac->txctl); > - > - /* Dump data structures if we're debugging */ > - dump_dev(dev); > - dump_rx_descriptor_queue(dev); > - dump_rx_status_queue(dev); > - dump_tx_descriptor_queue(dev); > - dump_tx_status_queue(dev); > - > - debug("-ep93xx_eth_open"); > - > - return 1; > -} > - > -/** > - * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL > - * registers. > - */ > -static void ep93xx_eth_close(struct eth_device *dev) > -{ > - struct mac_regs *mac = GET_REGS(dev); > - > - debug("+ep93xx_eth_close"); > - > - writel(0x00000000, &mac->rxctl); > - writel(0x00000000, &mac->txctl); > - > - debug("-ep93xx_eth_close"); > -} > - > -/** > - * Copy a frame of data from the MAC into the protocol layer for further > - * processing. > - */ > -static int ep93xx_eth_rcv_packet(struct eth_device *dev) > -{ > - struct mac_regs *mac = GET_REGS(dev); > - struct ep93xx_priv *priv = GET_PRIV(dev); > - int len = -1; > - > - debug("+ep93xx_eth_rcv_packet"); > - > - if (RX_STATUS_RFP(priv->rx_sq.current)) { > - if (RX_STATUS_RWE(priv->rx_sq.current)) { > - /* > - * We have a good frame. Extract the frame's length > - * from the current rx_status_queue entry, and copy > - * the frame's data into NetRxPackets[] of the > - * protocol stack. We track the total number of > - * bytes in the frame (nbytes_frame) which will be > - * used when we pass the data off to the protocol > - * layer via NetReceive(). > - */ > - len = RX_STATUS_FRAME_LEN(priv->rx_sq.current); > - > - NetReceive((uchar *)priv->rx_dq.current->word1, len); > - > - debug("reporting %d bytes...\n", len); > - } else { > - /* Do we have an erroneous packet? */ > - error("packet rx error, status %08X %08X", > - priv->rx_sq.current->word1, > - priv->rx_sq.current->word2); > - dump_rx_descriptor_queue(dev); > - dump_rx_status_queue(dev); > - } > - > - /* > - * Clear the associated status queue entry, and > - * increment our current pointers to the next RX > - * descriptor and status queue entries (making sure > - * we wrap properly). > - */ > - memset((void *)priv->rx_sq.current, 0, > - sizeof(struct rx_status)); > - > - priv->rx_sq.current++; > - if (priv->rx_sq.current >= priv->rx_sq.end) > - priv->rx_sq.current = priv->rx_sq.base; > - > - priv->rx_dq.current++; > - if (priv->rx_dq.current >= priv->rx_dq.end) > - priv->rx_dq.current = priv->rx_dq.base; > - > - /* > - * Finally, return the RX descriptor and status entries > - * back to the MAC engine, and loop again, checking for > - * more descriptors to process. > - */ > - writel(1, &mac->rxdqenq); > - writel(1, &mac->rxstsqenq); > - } else { > - len = 0; > - } > - > - debug("-ep93xx_eth_rcv_packet %d", len); > - return len; > -} > - > -/** > - * Send a block of data via ethernet. > - */ > -static int ep93xx_eth_send_packet(struct eth_device *dev, > - void * const packet, int const length) > -{ > - struct mac_regs *mac = GET_REGS(dev); > - struct ep93xx_priv *priv = GET_PRIV(dev); > - int ret = -1; > - > - debug("+ep93xx_eth_send_packet"); > - > - /* Parameter check */ > - BUG_ON(packet == NULL); > - > - /* > - * Initialize the TX descriptor queue with the new packet's info. > - * Clear the associated status queue entry. Enqueue the packet > - * to the MAC for transmission. > - */ > - > - /* set buffer address */ > - priv->tx_dq.current->word1 = (uint32_t)packet; > - > - /* set buffer length and EOF bit */ > - priv->tx_dq.current->word2 = length | TX_DESC_EOF; > - > - /* clear tx status */ > - priv->tx_sq.current->word1 = 0; > - > - /* enqueue the TX descriptor */ > - writel(1, &mac->txdqenq); > - > - /* wait for the frame to become processed */ > - while (!TX_STATUS_TXFP(priv->tx_sq.current)) > - ; /* noop */ > - > - if (!TX_STATUS_TXWE(priv->tx_sq.current)) { > - error("packet tx error, status %08X", > - priv->tx_sq.current->word1); > - dump_tx_descriptor_queue(dev); > - dump_tx_status_queue(dev); > - > - /* TODO: Add better error handling? */ > - goto eth_send_out; > - } > - > - ret = 0; > - /* Fall through */ > - > -eth_send_out: > - debug("-ep93xx_eth_send_packet %d", ret); > - return ret; > -} > - > -#if defined(CONFIG_MII) > -int ep93xx_miiphy_initialize(bd_t * const bd) > -{ > - miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, > ep93xx_miiphy_write); > - return 0; > -} > -#endif > - > -/** > - * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are > - * allocated, if necessary, for the TX and RX descriptor and status queues, > - * as well as for received packets. The EP93XX MAC hardware is initialized. > - * Transmit and receive operations are enabled. > - */ > -int ep93xx_eth_initialize(u8 dev_num, int base_addr) > -{ > - int ret = -1; > - struct eth_device *dev; > - struct ep93xx_priv *priv; > - > - debug("+ep93xx_eth_initialize"); > - > - priv = malloc(sizeof(*priv)); > - if (!priv) { > - error("malloc() failed"); > - goto eth_init_failed_0; > - } > - memset(priv, 0, sizeof(*priv)); > - > - priv->regs = (struct mac_regs *)base_addr; > - > - priv->tx_dq.base = calloc(NUMTXDESC, > - sizeof(struct tx_descriptor)); > - if (priv->tx_dq.base == NULL) { > - error("calloc() failed"); > - goto eth_init_failed_1; > - } > - > - priv->tx_sq.base = calloc(NUMTXDESC, > - sizeof(struct tx_status)); > - if (priv->tx_sq.base == NULL) { > - error("calloc() failed"); > - goto eth_init_failed_2; > - } > - > - priv->rx_dq.base = calloc(NUMRXDESC, > - sizeof(struct rx_descriptor)); > - if (priv->rx_dq.base == NULL) { > - error("calloc() failed"); > - goto eth_init_failed_3; > - } > - > - priv->rx_sq.base = calloc(NUMRXDESC, > - sizeof(struct rx_status)); > - if (priv->rx_sq.base == NULL) { > - error("calloc() failed"); > - goto eth_init_failed_4; > - } > - > - dev = malloc(sizeof *dev); > - if (dev == NULL) { > - error("malloc() failed"); > - goto eth_init_failed_5; > - } > - memset(dev, 0, sizeof *dev); > - > - dev->iobase = base_addr; > - dev->priv = priv; > - dev->init = ep93xx_eth_open; > - dev->halt = ep93xx_eth_close; > - dev->send = ep93xx_eth_send_packet; > - dev->recv = ep93xx_eth_rcv_packet; > - > - sprintf(dev->name, "ep93xx_eth-%hu", dev_num); > - > - eth_register(dev); > - > - /* Done! */ > - ret = 1; > - goto eth_init_done; > - > -eth_init_failed_5: > - free(priv->rx_sq.base); > - /* Fall through */ > - > -eth_init_failed_4: > - free(priv->rx_dq.base); > - /* Fall through */ > - > -eth_init_failed_3: > - free(priv->tx_sq.base); > - /* Fall through */ > - > -eth_init_failed_2: > - free(priv->tx_dq.base); > - /* Fall through */ > - > -eth_init_failed_1: > - free(priv); > - /* Fall through */ > - > -eth_init_failed_0: > - /* Fall through */ > - > -eth_init_done: > - debug("-ep93xx_eth_initialize %d", ret); > - return ret; > -} > - > -#if defined(CONFIG_MII) > - > -/** > - * Maximum MII address we support > - */ > -#define MII_ADDRESS_MAX 31 > - > -/** > - * Maximum MII register address we support > - */ > -#define MII_REGISTER_MAX 31 > - > -/** > - * Read a 16-bit value from an MII register. > - */ > -static int ep93xx_miiphy_read(const char * const dev, unsigned char const > addr, > - unsigned char const reg, unsigned short * const value) > -{ > - struct mac_regs *mac = (struct mac_regs *)MAC_BASE; > - int ret = -1; > - uint32_t self_ctl; > - > - debug("+ep93xx_miiphy_read"); > - > - /* Parameter checks */ > - BUG_ON(dev == NULL); > - BUG_ON(addr > MII_ADDRESS_MAX); > - BUG_ON(reg > MII_REGISTER_MAX); > - BUG_ON(value == NULL); > - > - /* > - * Save the current SelfCTL register value. Set MAC to suppress > - * preamble bits. Wait for any previous MII command to complete > - * before issuing the new command. > - */ > - self_ctl = readl(&mac->selfctl); > -#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) > - writel(self_ctl & ~(1 << 8), &mac->selfctl); > -#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ > - > - while (readl(&mac->miists) & MIISTS_BUSY) > - ; /* noop */ > - > - /* > - * Issue the MII 'read' command. Wait for the command to complete. > - * Read the MII data value. > - */ > - writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg, > - &mac->miicmd); > - while (readl(&mac->miists) & MIISTS_BUSY) > - ; /* noop */ > - > - *value = (unsigned short)readl(&mac->miidata); > - > - /* Restore the saved SelfCTL value and return. */ > - writel(self_ctl, &mac->selfctl); > - > - ret = 0; > - /* Fall through */ > - > - debug("-ep93xx_miiphy_read"); > - return ret; > -} > - > -/** > - * Write a 16-bit value to an MII register. > - */ > -static int ep93xx_miiphy_write(const char * const dev, unsigned char const > addr, > - unsigned char const reg, unsigned short const value) > -{ > - struct mac_regs *mac = (struct mac_regs *)MAC_BASE; > - int ret = -1; > - uint32_t self_ctl; > - > - debug("+ep93xx_miiphy_write"); > - > - /* Parameter checks */ > - BUG_ON(dev == NULL); > - BUG_ON(addr > MII_ADDRESS_MAX); > - BUG_ON(reg > MII_REGISTER_MAX); > - > - /* > - * Save the current SelfCTL register value. Set MAC to suppress > - * preamble bits. Wait for any previous MII command to complete > - * before issuing the new command. > - */ > - self_ctl = readl(&mac->selfctl); > -#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) > - writel(self_ctl & ~(1 << 8), &mac->selfctl); > -#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ > - > - while (readl(&mac->miists) & MIISTS_BUSY) > - ; /* noop */ > - > - /* Issue the MII 'write' command. Wait for the command to complete. > */ > - writel((uint32_t)value, &mac->miidata); > - writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg, > - &mac->miicmd); > - while (readl(&mac->miists) & MIISTS_BUSY) > - ; /* noop */ > - > - /* Restore the saved SelfCTL value and return. */ > - writel(self_ctl, &mac->selfctl); > - > - ret = 0; > - /* Fall through */ > - > - debug("-ep93xx_miiphy_write"); > - return ret; > -} > -#endif /* defined(CONFIG_MII) */ > diff --git a/drivers/net/ep93xx_eth.h b/drivers/net/ep93xx_eth.h > deleted file mode 100644 > index e6c949f..0000000 > --- a/drivers/net/ep93xx_eth.h > +++ /dev/null > @@ -1,127 +0,0 @@ > -/* > - * Copyright (C) 2009 Matthias Kaehlcke <matth...@kaehlcke.net> > - * > - * Copyright (C) 2004, 2005 > - * Cory T. Tusar, Videon Central, Inc., <ctu...@videon-central.com> > - * > - * SPDX-License-Identifier: GPL-2.0+ > - */ > - > -#ifndef _EP93XX_ETH_H > -#define _EP93XX_ETH_H > - > -#include <net.h> > - > -/** > - * #define this to dump device status and queue info during initialization > and > - * following errors. > - */ > -#undef EP93XX_MAC_DEBUG > - > -/** > - * Number of descriptor and status entries in our RX queues. > - * It must be power of 2 ! > - */ > -#define NUMRXDESC PKTBUFSRX > - > -/** > - * Number of descriptor and status entries in our TX queues. > - */ > -#define NUMTXDESC 1 > - > -/** > - * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT) > - */ > -#define TXSTARTMAX 944 > - > -/** > - * Receive descriptor queue entry > - */ > -struct rx_descriptor { > - uint32_t word1; > - uint32_t word2; > -}; > - > -/** > - * Receive status queue entry > - */ > -struct rx_status { > - uint32_t word1; > - uint32_t word2; > -}; > - > -#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01) > -#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01) > -#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF) > - > -/** > - * Transmit descriptor queue entry > - */ > -struct tx_descriptor { > - uint32_t word1; > - uint32_t word2; > -}; > - > -#define TX_DESC_EOF (1 << 31) > - > -/** > - * Transmit status queue entry > - */ > -struct tx_status { > - uint32_t word1; > -}; > - > -#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01) > -#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01) > - > -/** > - * Transmit descriptor queue > - */ > -struct tx_descriptor_queue { > - struct tx_descriptor *base; > - struct tx_descriptor *current; > - struct tx_descriptor *end; > -}; > - > -/** > - * Transmit status queue > - */ > -struct tx_status_queue { > - struct tx_status *base; > - volatile struct tx_status *current; > - struct tx_status *end; > -}; > - > -/** > - * Receive descriptor queue > - */ > -struct rx_descriptor_queue { > - struct rx_descriptor *base; > - struct rx_descriptor *current; > - struct rx_descriptor *end; > -}; > - > -/** > - * Receive status queue > - */ > -struct rx_status_queue { > - struct rx_status *base; > - volatile struct rx_status *current; > - struct rx_status *end; > -}; > - > -/** > - * EP93xx MAC private data structure > - */ > -struct ep93xx_priv { > - struct rx_descriptor_queue rx_dq; > - struct rx_status_queue rx_sq; > - void *rx_buffer[NUMRXDESC]; > - > - struct tx_descriptor_queue tx_dq; > - struct tx_status_queue tx_sq; > - > - struct mac_regs *regs; > -}; > - > -#endif > diff --git a/include/common.h b/include/common.h > index 8addf43..0764fac 100644 > --- a/include/common.h > +++ b/include/common.h > @@ -659,8 +659,7 @@ ulong get_OPB_freq (void); > ulong get_PCI_freq (void); > #endif > #if defined(CONFIG_S3C24X0) || \ > - defined(CONFIG_LH7A40X) || \ > - defined(CONFIG_EP93XX) > + defined(CONFIG_LH7A40X) > ulong get_FCLK (void); > ulong get_HCLK (void); > ulong get_PCLK (void); > diff --git a/include/netdev.h b/include/netdev.h > index 47fa80d..c0dbf70 100644 > --- a/include/netdev.h > +++ b/include/netdev.h > @@ -43,7 +43,6 @@ int e1000_initialize(bd_t *bis); > int eepro100_initialize(bd_t *bis); > int enc28j60_initialize(unsigned int bus, unsigned int cs, > unsigned int max_hz, unsigned int mode); > -int ep93xx_eth_initialize(u8 dev_num, int base_addr); > int eth_3com_initialize (bd_t * bis); > int ethoc_initialize(u8 dev_num, int base_addr); > int fec_initialize (bd_t *bis); > -- > 1.8.1.2 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot