Thierry, Your 3 patches (Avionics maintainer change, as well as the 2-part T114 MNP/CPCON changes) have been applied to u-boot-tegra/next, built, and tested on Dalmore.
New code (rebased against ARM/master) is available in both u-boot-tegra/next and /master, in anticipation of a pull request to u-boot-arm/master RSN. Thanks, Tom On Tue, Oct 1, 2013 at 8:06 AM, Thierry Reding <thierry.red...@gmail.com>wrote: > On Mon, Sep 30, 2013 at 02:25:57PM -0700, Tom Warren wrote: > > Thierry, > > > > > -----Original Message----- > > > From: Thierry Reding [mailto:thierry.red...@gmail.com] > > > Sent: Monday, September 23, 2013 1:08 PM > > > To: Tom Warren > > > Cc: u-boot@lists.denx.de > > > Subject: [PATCH v2 2/2] Tegra114: Do not program CPCON field for PLLX > > > > > > PLLX no longer has the CPCON field on Tegra114, so do not attempt to > > > program it. > > > > > > Signed-off-by: Thierry Reding <tred...@nvidia.com> > > > --- > > > Changes in v2: > > > - new patch > > > > > > arch/arm/cpu/arm720t/tegra-common/cpu.c | 4 +++- > > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c > > > b/arch/arm/cpu/arm720t/tegra-common/cpu.c > > > index aa1e04f..5ab2ebf 100644 > > > --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c > > > +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c > > > @@ -135,6 +135,7 @@ void adjust_pllp_out_freqs(void) int > > > pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, > > > u32 divp, u32 cpcon) > > > { > > > + int chip = tegra_get_chip(); > > > u32 reg; > > > > > > /* If PLLX is already enabled, just return */ @@ -151,7 +152,8 @@ > int > > > pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, > > > writel(reg, &pll->pll_base); > > > > > > /* Set cpcon to PLLX_MISC */ > > > - reg = (cpcon << PLL_CPCON_SHIFT); > > > + if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) > > > + reg = (cpcon << PLL_CPCON_SHIFT); > > If it's not a T20/T30, reg is still set to the PLLX_BASE setting from > above. It'll then be written to PLLX_MISC w/bad bits below. > > You need to set a default, or read pllx_misc first. > > Ugh... you're right of course. Sent a v3 with reg = 0 in the else > branch. > > Thanks, > Thierry >
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