These files are used by both SPL and main U-Boot.
Change-Id: I5b762fc3f9886f588372c7706feaf80c50305c75
Signed-off-by: Tom Warren <twar...@nvidia.com>
---
arch/arm/cpu/tegra-common/ap.c | 11 +++++++++--
arch/arm/cpu/tegra-common/board.c | 8 +++++++-
arch/arm/cpu/tegra-common/cache.c | 38 +++++++++++++++-----------------------
3 files changed, 31 insertions(+), 26 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 6fb11cb..c2c4a0b 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -27,7 +27,7 @@ int tegra_get_chip(void)
/*
* This is undocumented, Chip ID is bits 15:8 of the register
* APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
- * Tegra30, and 0x35 for T114.
+ * Tegra30, 0x35 for T114 and 0x40 for T124.
*/
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
debug("%s: CHIPID is 0x%02X\n", __func__, rev);
@@ -81,7 +81,14 @@ int tegra_get_chip_sku(void)
return TEGRA_SOC_T114;
}
break;
+ case CHIPID_TEGRA124:
+ switch (sku_id) {
+ }
+ case SKU_ID_T124_ENG:
+ return TEGRA_SOC_T124;
+ break;
}
+
/* unknown chip/sku id */
printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
__func__, chip_id, sku_id);
@@ -117,7 +124,7 @@ static u32 get_odmdata(void)
* The BCT start and size are stored in the BIT in IRAM.
* Read the data @ bct_start + (bct_size - 12). This works
* on T20 and T30 BCTs, which are locked down. If this changes
- * in new chips (T114, etc.), we can revisit this algorithm.
+ * in new chips (T1x4, etc.), we can revisit this algorithm.
*/
u32 bct_start, odmdata;
diff --git a/arch/arm/cpu/tegra-common/board.c
b/arch/arm/cpu/tegra-common/board.c
index d9cbda8..2c9613e 100644
--- a/arch/arm/cpu/tegra-common/board.c
+++ b/arch/arm/cpu/tegra-common/board.c
@@ -109,12 +109,18 @@ static int uart_configs[] = {
-1,
-1,
-1,
-#else /* Tegra114 */
+#elif defined(CONFIG_TEGRA114)
-1,
-1,
-1,
FUNCMUX_UART4_GMI, /* UARTD */
-1,
+#else /* Tegra12x */
+ FUNCMUX_UART1_KBC, /* UARTA */
+ -1,
+ -1,
+ FUNCMUX_UART4_GPIO, /* UARTD */
+ -1,
#endif
};
diff --git a/arch/arm/cpu/tegra-common/cache.c
b/arch/arm/cpu/tegra-common/cache.c
index 48e9319..11fe960 100644
--- a/arch/arm/cpu/tegra-common/cache.c
+++ b/arch/arm/cpu/tegra-common/cache.c
@@ -1,17 +1,8 @@
/*
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra cache routines */
@@ -33,16 +24,17 @@ void config_cache(void)
"orr r0, r0, #0x41\n"
"mcr p15, 0, r0, c1, c0, 1\n");
- /* Currently, only T114 needs this L2 cache change to boot Linux */
+ /* Currently, only T1x4 needs this L2 cache change to boot Linux */
reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
- if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
- return;
- /*
- * Systems with an architectural L2 cache must not use the PL310.
- * Config L2CTLR here for a data RAM latency of 3 cycles.
- */
- asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
- reg &= ~7;
- reg |= 2;
- asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
+ reg = (reg >> HIDREV_CHIPID_SHIFT) & 0xFF;
+ if ((reg == CHIPID_TEGRA114) || (reg == CHIPID_TEGRA124)) {
+ /*
+ * SoCs with an architectural L2 cache must not use the PL310.
+ * Config L2CTLR here for a data RAM latency of 3 cycles.
+ */
+ asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
+ reg &= ~7;
+ reg |= 2;
+ asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
+ }
}
--
1.8.1.5
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