Sure. My complete phys addresses mapping: DDR_SDRAM_BASE: 0x00000000 - 0x80000000 (2Gb) NAND: 0x80000000 - 0xc0000000 (1Gb) PCI1: 0xc0000000 - 0xd0000000 (256Mb) FPGA: 0xd0000000 - 0xd0100000 (1Mb) CCSRBAR (= PHYS): 0xe0000000 - 0xe4000000 (64Mb) PCI_IO: 0xe3000000 - 0xe3100000 (1Mb) INIT_RAM: 0xe4010000 CCSRBAR_DEFAULT: 0xff700000 BOOT_BLOCK=FLASH_BASE: 0xfff80000 - 0xffffffff (512Kb) (TEXT_BASE=FLASH_BASE + 0x10000)
RIO, CADMUS, PCIE and PCI2 are undefined. My law.c: - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(0x00000000, LAW_SIZE_512M, LAW_TRGT_IF_DDR), and NAND, FPGA windows (and PCI was resized to 256Mb). My tlb.c: SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), + 0, 0, BOOKE_PAGESZ_1M, 1), SDRAM and CADMUS was changed by FPGA and NAND tlbs (and PCI was resized to 256Mb). (nor) #define CONFIG_SYS_BR0_PRELIM 0xfff81001 #define CONFIG_SYS_OR0_PRELIM 0xfff80e65 (fpga) #define CONFIG_SYS_BR1_PRELIM 0xd0000801 #define CONFIG_SYS_OR1_PRELIM 0xfff06633 (nand) #define CONFIG_SYS_BR2_PRELIM 0x80000801 #define CONFIG_SYS_OR2_PRELIM 0xc0008ef7 Something must be very wrong. Recently I tried to change my 512kb NOR by a 1Mb NOR and some accesses to fff00000 to fff80000 addresses range hangs my processor (fff80000 to ffffffff works fine), but it can be a problem in my flash driver. Thanks for your help, Werner Nedel. On Thu, Apr 16, 2009 at 8:12 PM, Kumar Gala <ga...@kernel.crashing.org>wrote: > > On Apr 9, 2009, at 1:03 PM, Werner Nedel wrote: > > >> I'm trying to update my u-boot version (1.2) to the last one (2009.03). My >> board is very similar to MPC8548CDS. Everything was working fine till I >> tried to use the reset command. It hangs the processor in >> cpu_init_early_f, >> when it realocates ccsbar. I'd always used the hard reset in DBCR0 >> register >> instead HRESET_REQ that ins't wired in my board. >> >> I saw that the value of MSR register came different before reset when I >> compare with the old u-boot (0x8000 -> 0x29200). There are new writes in >> this register in this new version, could any of them causing my problem? >> > > It would probably be useful to have any obvious differences in the physical > address space from the MPC8548CDS config that exist. > > - k >
_______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot