As the DBGU and PIT has its own ID on sama5d3 SoC, while not share
with SYS ID. So, correct them.
Signed-off-by: Bo Shen <voice.s...@atmel.com>
---
arch/arm/cpu/armv7/at91/sama5d3_devices.c | 2 +-
arch/arm/cpu/armv7/at91/timer.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c
b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
index 51f0a6d..ebe99d2 100644
--- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c
+++ b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
@@ -82,7 +82,7 @@ void at91_seriald_hw_init(void)
at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */
/* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_SYS);
+ at91_periph_clk_enable(ATMEL_ID_DBGU);
}
#if defined(CONFIG_ATMEL_SPI)
diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c
index 3808aed..e3ebfe0 100644
--- a/arch/arm/cpu/armv7/at91/timer.c
+++ b/arch/arm/cpu/armv7/at91/timer.c
@@ -60,7 +60,7 @@ int timer_init(void)
at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
/* Enable PITC Clock */
- at91_periph_clk_enable(ATMEL_ID_SYS);
+ at91_periph_clk_enable(ATMEL_ID_PIT);
/* Enable PITC */
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
--
1.7.9.5
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