On Tue, Sep 10, 2013 at 12:55:06PM +0530, pekon gupta wrote: > With increase in NAND flash densities occurence of bit-flips has increased. > Thus stronger ECC schemes are required for detecting and correcting multiple > simultaneous bit-flips in same NAND page. But stronger ECC schemes have large > ECC syndrome which require more space in OOB/Spare. > This patch add support for BCH16_ECC: > (a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data. > (b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B. > > Due to (b) this scheme can only be used with NAND devices which have enough > OOB to satisfy following equation: > OOBsize per page >= 26 * (page-size / 512) > > Signed-off-by: Pekon Gupta <pe...@ti.com> > > --- > arch/arm/cpu/armv7/am33xx/elm.c | 95 ++++++++++++++++++++++------------ > arch/arm/include/asm/arch-am33xx/elm.h | 16 +++--- > 2 files changed, 69 insertions(+), 42 deletions(-)
omap_gpmc.c: In function 'omap_correct_data_bch': omap_gpmc.c:550:19: error: conversion to incomplete type It looks like this is fixed in patch 2/3, but this breaks bisectability. Also, does this code really belong under arch/arm rather than drivers/mtd/nand? -Scott _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
