Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.
Signed-off-by: Sourav Poddar <sourav.pod...@ti.com>
---
Hi Jagan,
This patch seems to be necessary for read/write.
I tested by changing few timing variables, but it did not help.
The same driver works on J6 with a differnet flash(S25FL256S).
Is any one tested macronix flash at uboot?
drivers/spi/ti_qspi.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 5666250..aa7b6ae 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -285,6 +285,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout,
qslave->cmd |= QSPI_3_PIN;
qslave->cmd |= 0xfff;
+#ifdef CONFIG_AM43XX
+ udelay(100);
+#endif
while (words--) {
if (txp) {
debug("tx cmd %08x dc %08x data %02x\n",
--
1.7.1
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