On Fri, Nov 08, 2013 at 05:40:37PM +0530, SRICHARAN R wrote: > Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using > software leveling. This was done since hardware leveling was not > working. Now that the right sequence to do hw leveling is identified, > use it. This is required for EMIF clockdomain to idle and come back > during lowpower usecases. > > Signed-off-by: Sricharan R <r.sricha...@ti.com>
Applied to u-boot-ti/master, thanks! -- Tom
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