On Sat, Dec 14, 2013 at 10:25 AM, Marek Vasut <ma...@denx.de> wrote: > Split the SATA clock enabling function and add PCI express clock > enabling function. The SATA clock enabling function starts up the > 100MHz SATA reference PLL in ENET_PLL register, but the code can > be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull > this code into separate function. Moreover, add the PCIe clock > enabling code. > > Signed-off-by: Marek Vasut <ma...@denx.de> > Cc: Albert Aribaud <albert.u.b...@aribaud.net> > Cc: Eric Nelson <eric.nel...@boundarydevices.com> > Cc: Fabio Estevam <fabio.este...@freescale.com> > Cc: Stefano Babic <sba...@denx.de> > --- > arch/arm/cpu/armv7/mx6/clock.c | 75 > ++++++++++++++++++++++++++++++----- > arch/arm/include/asm/arch-mx6/clock.h | 1 + > 2 files changed, 66 insertions(+), 10 deletions(-) > > V2: Drop the clock teardown function, it is not needed. Instead, fix a patch > for the Linux kernel to handle running link. > > diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c > index 873d9d0..b25a954 100644 > --- a/arch/arm/cpu/armv7/mx6/clock.c > +++ b/arch/arm/cpu/armv7/mx6/clock.c > @@ -404,17 +404,12 @@ u32 imx_get_fecclk(void) > return decode_pll(PLL_ENET, MXC_HCLK); > } > > -int enable_sata_clock(void) > +static int enable_enet_pll(uint32_t en) > { > - u32 reg = 0; > - s32 timeout = 100000; > struct mxc_ccm_reg *const imx_ccm > = (struct mxc_ccm_reg *) CCM_BASE_ADDR; > - > - /* Enable sata clock */ > - reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ > - reg |= MXC_CCM_CCGR5_SATA_MASK; > - writel(reg, &imx_ccm->CCGR5); > + s32 timeout = 100000; > + u32 reg = 0; > > /* Enable PLLs */ > reg = readl(&imx_ccm->analog_pll_enet); > @@ -429,10 +424,70 @@ int enable_sata_clock(void) > return -EIO; > reg &= ~BM_ANADIG_PLL_SYS_BYPASS; > writel(reg, &imx_ccm->analog_pll_enet); > - reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA; > + reg |= en; > writel(reg, &imx_ccm->analog_pll_enet); > + return 0; > +} > > - return 0 ; > +static void ungate_sata_clock(void) > +{ > + struct mxc_ccm_reg *const imx_ccm = > + (struct mxc_ccm_reg *) CCM_BASE_ADDR; Try to delete the space after a cast
> + > + /* Enable SATA clock. */ > + setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); > +} > + > +static void ungate_pcie_clock(void) > +{ > + struct mxc_ccm_reg *const imx_ccm = > + (struct mxc_ccm_reg *) CCM_BASE_ADDR; << same >> -- Thanks, Jagan. -------- Jagannadha Sutradharudu Teki, E: jagannadh.t...@gmail.com, P: +91-9676773388 Engineer - System Software Hacker U-boot - SPI Custodian and Zynq APSOC Ln: http://www.linkedin.com/in/jaganteki _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot