Erratum 71 of PXA270M Processor Family Specification Update
(April 19, 2010) explains that watchdog reset time is just
8us insead of 10ms in EMTS.
If SDRAM is not reset, it causes memory bus congestion and
the device hangs.
We put SDRAM in selfresh mode before watchdog reset, removing
potential freezes.
Signed-off-by: Sergei Ianovich <ynv...@gmail.com>
---
arch/arm/cpu/pxa/pxa2xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
index c9a7d45..93ca2f0 100644
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -281,5 +281,5 @@ void reset_cpu(ulong ignored)
writel(tmp, OSMR3);
for (;;)
- ;
+ writel(MDREFR_SLFRSH, MDREFR);
}
--
1.8.4.2
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