On Thu, Dec 05, 2013 at 05:54:21PM +0530, pekon gupta wrote: > As per OMAP3530 TRM referenced below [1] > > For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme > - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device > - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device > > Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is: > *for x8 NAND Device* > +--------+---------+---------+---------+---------+---------+---------+ > | xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ... > +--------+---------+---------+---------+---------+---------+---------+ > > *for x16 NAND Device* > > +--------+--------+---------+---------+---------+---------+---------+---------+ > | xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | > ECC[B2] | > > +--------+--------+---------+---------+---------+---------+---------+---------+ > > This patch fixes ecc-layout *only* for HAM1, as required by ROM-code > For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices. > > [1] OMAP3530: http://www.ti.com/product/omap3530 > TRM: http://www.ti.com/litv/pdf/spruf98x > Chapter-25: Initialization Sub-topic: Memory Booting > Section: 25.4.7.4 NAND > Figure 25-19. ECC Locations in NAND Spare Areas > > Reported-by: Stefan Roese <s...@denx.de> > Signed-off-by: Pekon Gupta <pe...@ti.com> > Tested-by: Stefan Roese <s...@denx.de> > > --- > drivers/mtd/nand/omap_gpmc.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-)
Applied to u-boot-nand-flash.git -Scott _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot