Add L3 cache support and enable it by default.
Signed-off-by: Fabio Estevam <fabio.este...@freescale.com>
---
arch/arm/cpu/armv7/mx6/soc.c | 22 ++++++++++++++++++++++
include/configs/mx6_common.h | 5 +++++
2 files changed, 27 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 0208cba..5e1e5e9 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -8,6 +8,8 @@
*/
#include <common.h>
+#include <asm/armv7.h>
+#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
@@ -336,3 +338,23 @@ void imx_setup_hdmi(void)
writel(reg, &mxc_ccm->chsccdr);
}
#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define L2CACHE 1
+void v7_outer_cache_enable(void)
+{
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+ setbits_le32(&pl310->pl310_ctrl, L2CACHE);
+
+}
+
+void v7_outer_cache_disable(void)
+{
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+ clrbits_le32(&pl310->pl310_ctrl, L2CACHE);
+}
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 514d634..993eca1 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -22,4 +22,9 @@
#define CONFIG_ARM_ERRATA_751472
#define CONFIG_BOARD_POSTCLK_INIT
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE 0x00A02000
+#endif
+
#endif
--
1.8.1.2
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