Hi Dirk, On 28/01/2014 17:53, Dirk Behme wrote:
> > Just for better understanding: Do you want to keep this intentionally > simple? Or is there any special reason why you don't set additional > (performance) registers here? E.g. the L2 PREFETCH and POWER registers, > and the tag and data latency settings? Like done in the kernel. This is a good point ! If it is true that L2 PREFETCH is turned on in mainline kernel, but it was *explicitely* turned off by Jason in FSL Kernel with the patch with subject ENGR00278489 (ARM PL310 errata: 7522719). It seems to me that Fabio has already applied Jason's patch - maybe should we check as in FSL kernel which i.MX6 is running (DL and Solo are not affected). Jason, can you a little explain this topic ? Was the patch sent to Shaw, too (set in CC) ? Thanks, Stefano -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot