On Tuesday, February 04, 2014 at 10:49:24 PM, Lukasz Majewski wrote: [...]
> > > Maybe other ARM architectures shall have the cache management code > > > updated to work in a similar way to cache_v7.c ? > > > > Not all CPUs are ARM architecture ... there're others, you know ;-) > : > :-) ... but who cares about the rest :-) Me, duh. I have mips, sparc and m68k devices here and I'm not afraid to use them! > To be serious (quite), I do believe that checking if unaligned > cache flush/invalidation is performed, shall be handled at the code > which is responsible for cache management. > > Conceptually, it shall not be done at UDC code. You have a point, ACK. Even better, we should have a wrapper for that which will only then call the cache management routine. [...] Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
