T1040 has internal display interface unit (DIU) for driving video.
T1040QDS supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder

Chrontel, CH7301C encoder which is I2C programmable is used as
HDMI connector on T1040QDS.
This patch add support to
-enable Video interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board

Signed-off-by: Priyanka Jain <priyanka.j...@freescale.com>
---
 Changes for v2: Fix compilation warnings

 board/freescale/t1040qds/Makefile         |    1 +
 board/freescale/t1040qds/diu.c            |  215 +++++++++++++++++++++++++++++
 board/freescale/t1040qds/t1040qds.h       |    1 +
 board/freescale/t1040qds/t1040qds_qixis.h |   12 ++
 include/configs/T1040QDS.h                |   27 ++++-
 5 files changed, 255 insertions(+), 1 deletions(-)
 create mode 100644 board/freescale/t1040qds/diu.c

diff --git a/board/freescale/t1040qds/Makefile 
b/board/freescale/t1040qds/Makefile
index c7470d7..19ed21b 100644
--- a/board/freescale/t1040qds/Makefile
+++ b/board/freescale/t1040qds/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PCI)     += pci.o
 obj-y  += law.o
 obj-y  += tlb.o
 obj-y  += eth.o
+obj-y  += diu.o
diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c
new file mode 100644
index 0000000..ffd074b
--- /dev/null
+++ b/board/freescale/t1040qds/diu.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Priyanka Jain <priyanka.j...@freescale.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <video_fb.h>
+#include <fsl_diu_fb.h>
+#include "../common/qixis.h"
+#include "t1040qds.h"
+#include "t1040qds_qixis.h"
+#include <i2c.h>
+
+
+#define I2C_DVI_INPUT_DATA_FORMAT_REG          0x1F
+#define I2C_DVI_PLL_CHARGE_CNTL_REG            0x33
+#define I2C_DVI_PLL_DIVIDER_REG                        0x34
+#define I2C_DVI_PLL_SUPPLY_CNTL_REG            0x35
+#define I2C_DVI_PLL_FILTER_REG                 0x36
+#define I2C_DVI_TEST_PATTERN_REG               0x48
+#define I2C_DVI_POWER_MGMT_REG                 0x49
+#define I2C_DVI_LOCK_STATE_REG                 0x4D
+#define I2C_DVI_SYNC_POLARITY_REG              0x56
+
+/*
+ * Set VSYNC/HSYNC to active high. This is polarity of sync signals
+ * from DIU->DVI. The DIU default is active igh, so DVI is set to
+ * active high.
+ */
+#define I2C_DVI_INPUT_DATA_FORMAT_VAL          0x98
+
+#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
+#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL     0x26
+#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL      0xA0
+#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL  0x08
+#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL      0x16
+#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL       0x60
+
+/* Clear test pattern */
+#define I2C_DVI_TEST_PATTERN_VAL               0x18
+/* Exit Power-down mode */
+#define I2C_DVI_POWER_MGMT_VAL                 0xC0
+
+/* Monitor polarity is handled via DVI Sync Polarity Register */
+#define I2C_DVI_SYNC_POLARITY_VAL              0x00
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register.  So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F              0x10000000
+#define AD_ALPHA_C_SHIFT       25
+#define AD_BLUE_C_SHIFT                23
+#define AD_GREEN_C_SHIFT       21
+#define AD_RED_C_SHIFT         19
+#define AD_PIXEL_S_SHIFT       16
+#define AD_COMP_3_SHIFT                12
+#define AD_COMP_2_SHIFT                8
+#define AD_COMP_1_SHIFT                4
+#define AD_COMP_0_SHIFT                0
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock)
+{
+       int ret;
+       u8 temp;
+       select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
+
+       temp = I2C_DVI_TEST_PATTERN_VAL;
+       ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
+                       &temp, 1);
+       if (ret) {
+               puts("I2C: failed to select proper dvi test pattern\n");
+               return ret;
+       }
+       temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
+       ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
+                       1, &temp, 1);
+       if (ret) {
+               puts("I2C: failed to select dvi input data format\n");
+               return ret;
+       }
+
+       /* Set Sync polarity register */
+       temp = I2C_DVI_SYNC_POLARITY_VAL;
+       ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
+                       &temp, 1);
+       if (ret) {
+               puts("I2C: failed to select dvi syc polarity\n");
+               return ret;
+       }
+
+       /* Set PLL registers based on pixel clock rate*/
+       if (pixclock > 65000000) {
+               temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
+               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+                               I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+               if (ret) {
+                       puts("I2C: failed to select dvi pll charge_cntl\n");
+                       return ret;
+               }
+               temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
+               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+                               I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+               if (ret) {
+                       puts("I2C: failed to select dvi pll divider\n");
+                       return ret;
+               }
+               temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
+               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+                               I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+               if (ret) {
+                       puts("I2C: failed to select dvi pll filter\n");
+                       return ret;
+               }
+       } else {
+               temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
+               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+                               I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+               if (ret) {
+                       puts("I2C: failed to select dvi pll charge_cntl\n");
+                       return ret;
+               }
+               temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
+               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+                               I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+               if (ret) {
+                       puts("I2C: failed to select dvi pll divider\n");
+                       return ret;
+               }
+               temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
+               ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+                               I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+               if (ret) {
+                       puts("I2C: failed to select dvi pll filter\n");
+                       return ret;
+               }
+       }
+
+       temp = I2C_DVI_POWER_MGMT_VAL;
+       ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
+                       &temp, 1);
+       if (ret) {
+               puts("I2C: failed to select dvi power mgmt\n");
+               return ret;
+       }
+
+       udelay(500);
+
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+       return 0;
+}
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+       unsigned long speed_ccb, temp;
+       u32 pixval;
+       int ret = 0;
+       speed_ccb = get_bus_freq(0);
+       temp = 1000000000 / pixclock;
+       temp *= 1000;
+       pixval = speed_ccb / temp;
+
+       /* Program HDMI encoder */
+       ret = diu_set_dvi_encoder(temp);
+       if (ret) {
+               puts("Failed to set DVI encoder\n");
+               return;
+       }
+
+       /* Program pixel clock */
+       out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
+                ((pixval << PXCK_BITS_START) & PXCK_MASK));
+       /* enable clock*/
+       out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
+                ((pixval << PXCK_BITS_START) & PXCK_MASK));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+       u32 pixel_format;
+       u8 sw;
+
+       /*Route I2C4 to DIU system as HSYNC/VSYNC*/
+       sw = QIXIS_READ(brdcfg[5]);
+       QIXIS_WRITE(brdcfg[5],
+                   ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
+
+       /*Configure Display ouput port as HDMI*/
+       sw = QIXIS_READ(brdcfg[15]);
+       QIXIS_WRITE(brdcfg[15],
+                   ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
+                     | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
+
+       pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+               (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+               (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+               (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+               (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+       printf("DIU:   Switching to monitor @ %ux%u\n",  xres, yres);
+
+
+       return fsl_diu_init(xres, yres, pixel_format, 0);
+}
diff --git a/board/freescale/t1040qds/t1040qds.h 
b/board/freescale/t1040qds/t1040qds.h
index 79bdeda..5041f37 100644
--- a/board/freescale/t1040qds/t1040qds.h
+++ b/board/freescale/t1040qds/t1040qds.h
@@ -9,5 +9,6 @@
 
 void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, bd_t *bd);
+int select_i2c_ch_pca9547(u8 ch);
 
 #endif
diff --git a/board/freescale/t1040qds/t1040qds_qixis.h 
b/board/freescale/t1040qds/t1040qds_qixis.h
index 2ce8795..98d2d39 100644
--- a/board/freescale/t1040qds/t1040qds_qixis.h
+++ b/board/freescale/t1040qds/t1040qds_qixis.h
@@ -13,6 +13,18 @@
 #define BRDCFG4_EMISEL_MASK            0xE0
 #define BRDCFG4_EMISEL_SHIFT           5
 
+/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
+#define BRDCFG5_IMX_MASK               0xC0
+#define BRDCFG5_IMX_DIU                        0x80
+
+/* BRDCFG15[3] controls LCD Panel Powerdown*/
+#define BRDCFG15_LCDPD_MASK            0x10
+#define BRDCFG15_LCDPD_ENABLED         0x00
+
+/* BRDCFG15[6:7] controls DIU MUX selction*/
+#define BRDCFG15_DIUSEL_MASK           0x03
+#define BRDCFG15_DIUSEL_HDMI           0x00
+
 /* SYSCLK */
 #define QIXIS_SYSCLK_66                        0x0
 #define QIXIS_SYSCLK_83                        0x1
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 75ea125..3f26559 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -375,7 +375,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN          (4 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN          (10 * 1024 * 1024)
 
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
@@ -401,6 +401,25 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
+/* Video */
+#define CONFIG_FSL_DIU_FB
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR    (CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
@@ -426,6 +445,11 @@ unsigned long get_board_ddr_clk(void);
 
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT      0x8
+#define I2C_MUX_CH_DIU         0xC
+
+/* LDI/DVI Encoder for display */
+#define CONFIG_SYS_I2C_LDI_ADDR         0x38
+#define CONFIG_SYS_I2C_DVI_ADDR         0x75
 
 /*
  * RTC configuration
@@ -704,6 +728,7 @@ unsigned long get_board_ddr_clk(void);
        "bank_intlv=cs0_cs1;"                                   \
        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
        "netdev=eth0\0"                                         \
+       "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
        "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
        "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
        "tftpflash=tftpboot $loadaddr $uboot && "               \
-- 
1.7.4.1



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