Add support of 2-stage NAND boot loader using SPL framework on T2080RDB.
PBL initialise the internal SRAM and copy SPL(96K), this further
initialise DDR using SPD and environment and copy u-boot from NAND
to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Shengzhou Liu <shengzhou....@freescale.com>
---
board/freescale/t208xrdb/Makefile | 5 +++
board/freescale/t208xrdb/README | 8 ++--
board/freescale/t208xrdb/ddr.c | 7 ++-
board/freescale/t208xrdb/spl.c | 93 +++++++++++++++++++++++++++++++++++++++
board/freescale/t208xrdb/tlb.c | 4 +-
boards.cfg | 2 +-
include/configs/T208xRDB.h | 58 +++++++++++++++++++++---
7 files changed, 164 insertions(+), 13 deletions(-)
create mode 100644 board/freescale/t208xrdb/spl.c
diff --git a/board/freescale/t208xrdb/Makefile
b/board/freescale/t208xrdb/Makefile
index 092c9ff..9605f8b 100644
--- a/board/freescale/t208xrdb/Makefile
+++ b/board/freescale/t208xrdb/Makefile
@@ -4,10 +4,15 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-$(CONFIG_T2080RDB) += t208xrdb.o
obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
obj-$(CONFIG_T2080RDB) += cpld.o
obj-$(CONFIG_PCI) += pci.o
+endif
+
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README
index 0012c6c..dfa73ae 100644
--- a/board/freescale/t208xrdb/README
+++ b/board/freescale/t208xrdb/README
@@ -164,10 +164,10 @@ Software configurations and board settings
2. NAND Boot:
a. build PBL image for NAND boot
$ make T2080RDB_NAND_config
- $ make u-boot.pbl
- b. program u-boot.pbl to NAND flash
- => tftp 1000000 u-boot.pbl
- => nand erase 0 d0000
+ $ make u-boot-with-spl-pbl.bin
+ b. program u-boot-with-spl-pbl.bin to NAND flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => nand erase 0 c0000
=> nand write 1000000 0 $filesize
set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
index 01e9173..18c9abd 100644
--- a/board/freescale/t208xrdb/ddr.c
+++ b/board/freescale/t208xrdb/ddr.c
@@ -102,11 +102,14 @@ phys_size_t initdram(int board_type)
puts("Initializing....using SPD\n");
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
-
- puts(" DDR: ");
+#else
+ puts("DDR has been initialised by first stage boot loader\n");
+ dram_size = 0x80000000;
+#endif
return dram_size;
}
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
new file mode 100644
index 0000000..648481c
--- /dev/null
+++ b/board/freescale/t208xrdb/spl.c
@@ -0,0 +1,93 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/spl.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+ __asm__ __volatile__("" : : : "memory");
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+ env_init();
+#endif
+
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+#else
+ env_relocate();
+#endif
+
+ i2c_init_all();
+
+ puts("\n\n");
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
index 085d9f5..2ebea36 100644
--- a/board/freescale/t208xrdb/tlb.c
+++ b/board/freescale/t208xrdb/tlb.c
@@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCIe 1, 0x80000000 */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_16M, 1),
#endif
+#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -140,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 19, BOOKE_PAGESZ_2G, 1)
diff --git a/boards.cfg b/boards.cfg
index 2715a20..17d8133 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -986,7 +986,7 @@ Active powerpc mpc85xx - freescale
t208xqds
Active powerpc mpc85xx - freescale t208xrdb
T2080RDB T208xRDB:PPC_T2080
Active powerpc mpc85xx - freescale t208xrdb
T2080RDB_SDCARD
T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
Active powerpc mpc85xx - freescale t208xrdb
T2080RDB_SPIFLASH
T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
-Active powerpc mpc85xx - freescale t208xrdb
T2080RDB_NAND
T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xrdb
T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,RAMBOOT_SPLPBL,NAND
Active powerpc mpc85xx - freescale t208xrdb
T2080RDB_SRIO_PCIE_BOOT
T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
Active powerpc mpc85xx - freescale t4qds
T4160QDS T4240QDS:PPC_T4160
-
Active powerpc mpc85xx - freescale t4qds
T4160QDS_SDCARD
T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
-
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 979843b..f751689 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -39,10 +39,44 @@
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_FSL_PBL_PBI
$(SRCTREE)/board/freescale/t208xrdb/t2080_pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW
$(SRCTREE)/board/freescale/t208xrdb/t2080_rcw.cfg
+#ifndef CONFIG_NAND
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFD0000
+#define CONFIG_SPL_PAD_TO 0x40000
+#define CONFIG_SPL_MAX_SIZE 0x30000
+#define RESET_VECTOR_OFFSET 0x2FFFC
+#define BOOT_PAGE_OFFSET 0x2F000
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+#define CONFIG_RAMBOOT_TEXT_BASE 0xFFFE0000
+#endif
#endif
#define CONFIG_SRIO_PCIE_BOOT_MASTER
@@ -103,7 +137,7 @@
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
@@ -129,7 +163,16 @@ unsigned long get_board_ddr_clk(void);
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE (256 << 10)
+#define CONFIG_SPL_GD_ADDR CONFIG_SYS_INIT_L3_ADDR
+#ifdef CONFIG_NAND
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L3_ADDR + 4 *
1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L3_ADDR + 10 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L3_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (20 << 10)
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
@@ -301,7 +344,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
--
1.8.0
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