From: Fabio Estevam <fabio.este...@freescale.com>
On mx6sl there is a LVE (Low Voltage Enable) in the IOMUXC_SW_PAD_CTL register.
LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the
calculation easier we can define it as bit 17 as this bit is unused and fits the
current MUX_PAD_CTRL_MASK mask.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.este...@freescale.com>
---
arch/arm/imx-common/iomux-v3.c | 8 ++++++++
arch/arm/include/asm/imx-common/iomux-v3.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index b59b802..6e46ea8 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -30,6 +30,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+#if defined CONFIG_MX6SL
+ /* Check whether LVE bit needs to be set */
+ if (pad_ctrl & PAD_CTL_LVE) {
+ pad_ctrl &= ~PAD_CTL_LVE;
+ pad_ctrl |= PAD_CTL_LVE_BIT;
+ }
+#endif
+
if (mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h
b/arch/arm/include/asm/imx-common/iomux-v3.h
index dec11a1..6d3561f 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -88,6 +88,8 @@ typedef u64 iomux_v3_cfg_t;
#ifdef CONFIG_MX6
#define PAD_CTL_HYS (1 << 16)
+#define PAD_CTL_LVE (1 << 17)
+#define PAD_CTL_LVE_BIT (1 << 22)
#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE)
#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE)
--
1.8.3.2
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