On Tue, Jun 17, 2014 at 04:47:40PM +0200, Stefano Babic wrote: > gpmc timeout is disabled and the reset counter > is set to 0. However, if later a driver activates > the timeout setting the reset to a valid value, > the old reset value with zero is still valid > for the first access. In fact, the timeout block > loads the reset counter after a successful access. > > Found on a am335x board with a FPGA connected > to the GPMC bus together with the NAND. > When the FPGA driver in kernel activates > the timeout, the system hangs at the first access > by the NAND driver. > > Signed-off-by: Stefano Babic <sba...@denx.de>
Applied to u-boot-ti/master, thanks! -- Tom
signature.asc
Description: Digital signature
_______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
