From: Shaohui Xie <shaohui....@freescale.com>
NEG bit default is '1' for external MDIOs as per FMAN-v3 RM, but on some
platforms, e.g. T2080QDS, this bit is '0', which leads to MDIO failure
on XAUI PHY, so set this bit definitely to align with the RM.
Signed-off-by: Shaohui Xie <shaohui....@freescale.com>
---
arch/powerpc/include/asm/fsl_memac.h | 1 +
drivers/net/fm/memac_phy.c | 5 ++++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/fsl_memac.h
b/arch/powerpc/include/asm/fsl_memac.h
index 4640e33..190643e 100644
--- a/arch/powerpc/include/asm/fsl_memac.h
+++ b/arch/powerpc/include/asm/fsl_memac.h
@@ -243,6 +243,7 @@ struct memac_mdio_controller {
#define MDIO_STAT_PRE (1 << 5)
#define MDIO_STAT_ENC (1 << 6)
#define MDIO_STAT_HOLD_15_CLK (7 << 2)
+#define MDIO_STAT_NEG (1 << 23)
#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index de9c0e9..f5b20d5 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -137,9 +137,12 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info
*info)
* is zero, so MDIO clock is disabled.
* So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
* be properly initialized.
+ * NEG bit default should be '1' as per FMAN-v3 RM, but on platform
+ * like T2080QDS, this bit default is '0', which leads to MDIO failure
+ * on XAUI PHY, so set this bit definitely.
*/
setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
- MDIO_STAT_CLKDIV(258));
+ MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
return mdio_register(bus);
}
--
1.8.0
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