From: Hao Zhang <hzh...@ti.com> This patch adds Keystone II Lamar (K2L) SoC specific definitions to support MSMC cache coherency.
Acked-by: Vitaly Andrianov <vita...@ti.com> Signed-off-by: Hao Zhang <hzh...@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronz...@ti.com> --- arch/arm/cpu/armv7/keystone/init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index a8f8aee..a0ecfa2 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -32,6 +32,9 @@ int arch_cpu_init(void) #ifdef CONFIG_SOC_K2E msmc_share_all_segments(13); /* PCIE 1 */ #endif +#ifdef CONFIG_SOC_K2L + msmc_share_all_segments(14); /* PCIE 1 */ +#endif /* * just initialise the COM2 port so that TI specific -- 1.8.3.2 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot