This entire series is the second stab at making SoCFPGA usable with mainline U-Boot again. There are much fewer bits missing than in the last series, more cleanup happened and bugs were fixed. This allows me to use mainline U-Boot on my SoCFPGA systems.
The big missing part is the SPL generation, which still needs a lot of additional work. We also miss the Cadence QSPI controller driver. This set contains patches for a few subsystems, which are utilized by the SoCFPGA, but the most part is the SoCFPGA chip support. This series now contains cleanup for the mayhem in drivers/fpga/altera.c code, which was terrible, but is now much better. Charles Manning (1): tools: socfpga: Add socfpga preloader signing to mkimage Chin Liang See (2): arm: socfpga: Enable DWMMC for SOCFPGA arm: socfpga: Enable SDMMC boot for SOCFPGA U-Boot Marek Vasut (32): net: dwc: Fix cache alignment issues net: dwc: Make the cache handling less cryptic mmc: dw_mmc: Fix cache alignment issue arm: socfpga: Clean up base address file arm: socfpga: sysmgr: Clean up system manager arm: socfpga: clock: Implant order into bit definitions arm: socfpga: clock: Drop nonsense inlining from clock manager code arm: socfpga: clock: Add missing stubs into board file arm: socfpga: clock: Trim down code duplication arm: socfpga: clock: Clean up bit definitions arm: socfpga: clock: Sync with reference code arm: socfpga: timer: Pull the timer reload value from config file arm: socfpga: reset: Add EMAC reset functions arm: socfpga: board: Align checkboard() output fpga: altera: Clean up the printing and debug fpga: altera: Clean up altera_validate function fpga: altera: More indentation trimdown fpga: altera: Move altera_validate to the top fpga: altera: Make altera_validate return normal values fpga: altera: Clean up enums in altera.h fpga: altera: Turn the switches into table lookup arm: socfpga: reset: Add function to reset FPGA bridges arm: socfpga: sysmgr: Add FPGA bits into system manager arm: cache: Add support for write-allocate D-Cache arm: socfpga: cache: Define cacheline size arm: socfpga: cache: Enable D-Cache arm: socfpga: cache: Enable PL310 L2 cache arm: socfpga: scu: Add SCU register file arm: socfpga: nic301: Add NIC-301 GPV register file arm: socfpga: pl310: Map SDRAM to 0x0 arm: socfpga: Move cache_enable to CPU code arm: socfpga: Use CMD_FS_GENERIC Pavel Machek (16): net: Remove unused CONFIG_DW_SEARCH_PHY from configs net: phy: Cleanup drivers/net/phy/micrel.c mmc: dw_mmc: cleanups arm: socfpga: Complete the list of base addresses arm: socfpga: Add watchdog disable for socfpga arm: socfpga: clock: Add code to read clock configuration arm: socfpga: mmc: Pick the clock from clock manager arm: socfpga: misc: Add proper ethernet initialization arm: socfpga: misc: Add SD controller init arm: socfpga: misc: Align print_cpuinfo() output arm: socfpga: board: Correctly set ATAG position arm: socfpga: fpga: Add SoCFPGA FPGA programming interface arm: socfpga: nic301: Add NIC-301 configuration code arm: socfpga: Add command to control HPS-FPGA bridges arm: socfpga: Clean up SoCFPGA configuration arm: socfpga: Split SoCFPGA configuration arch/arm/cpu/armv7/socfpga/Makefile | 3 +- arch/arm/cpu/armv7/socfpga/clock_manager.c | 340 ++++++++++++++++----- arch/arm/cpu/armv7/socfpga/fpga_manager.c | 78 +++++ arch/arm/cpu/armv7/socfpga/misc.c | 235 +++++++++++++- arch/arm/cpu/armv7/socfpga/reset_manager.c | 67 ++++ arch/arm/cpu/armv7/socfpga/spl.c | 174 ++++++----- arch/arm/cpu/armv7/socfpga/system_manager.c | 57 +++- arch/arm/cpu/armv7/socfpga/timer.c | 2 + arch/arm/include/asm/arch-socfpga/clock_manager.h | 306 ++++++++++++------- arch/arm/include/asm/arch-socfpga/fpga_manager.h | 77 +++++ arch/arm/include/asm/arch-socfpga/nic301.h | 195 ++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 9 + arch/arm/include/asm/arch-socfpga/scu.h | 23 ++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 62 +++- arch/arm/include/asm/arch-socfpga/system_manager.h | 111 +++++-- arch/arm/include/asm/system.h | 1 + arch/arm/lib/cache-cp15.c | 2 + board/altera/socfpga/pll_config.h | 3 + board/altera/socfpga/socfpga_cyclone5.c | 6 +- common/image.c | 1 + drivers/fpga/Makefile | 1 + drivers/fpga/altera.c | 308 ++++++++----------- drivers/fpga/socfpga.c | 301 ++++++++++++++++++ drivers/mmc/dw_mmc.c | 34 ++- drivers/mmc/socfpga_dw_mmc.c | 15 +- drivers/net/designware.c | 46 +-- drivers/net/phy/micrel.c | 7 +- include/altera.h | 82 +++-- include/configs/axs101.h | 1 - include/configs/socfpga_cyclone5.h | 318 ++++--------------- include/configs/socfpga_cyclone5_common.h | 196 ++++++++++++ include/dwmmc.h | 2 +- include/image.h | 1 + tools/Makefile | 1 + tools/imagetool.c | 2 + tools/imagetool.h | 1 + tools/socfpgaimage.c | 255 ++++++++++++++++ 37 files changed, 2503 insertions(+), 820 deletions(-) create mode 100644 arch/arm/cpu/armv7/socfpga/fpga_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/fpga_manager.h create mode 100644 arch/arm/include/asm/arch-socfpga/nic301.h create mode 100644 arch/arm/include/asm/arch-socfpga/scu.h create mode 100644 drivers/fpga/socfpga.c create mode 100644 include/configs/socfpga_cyclone5_common.h create mode 100644 tools/socfpgaimage.c Cc: Chin Liang See <cl...@altera.com> Cc: Dinh Nguyen <dingu...@altera.com> Cc: Albert Aribaud <albert.u.b...@aribaud.net> Cc: Tom Rini <tr...@ti.com> Cc: Wolfgang Denk <w...@denx.de> Cc: Pavel Machek <pa...@denx.de> -- 2.0.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot