T2080 v1.0 has this errata while v1.1 has fixed
this errata by hardware, add a new function to
check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first,
if the cpu is T2080 and version is not v1.0, doesn't
run the a007186 errata_workaround.
Signed-off-by: Zhao Qiang <b45...@freescale.com>
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +-
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 210 ++++++++++++++-----------
arch/powerpc/include/asm/fsl_errata.h | 14 ++
3 files changed, 130 insertions(+), 97 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3a04a89..741eb63 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -270,7 +270,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
puts("Work-around for Erratum USB14 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
- puts("Work-around for Erratum A007186 enabled\n");
+ if (!not_has_erratum_a007186())
+ puts("Work-around for Erratum A007186 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
puts("Work-around for Erratum A006593 enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index d1fc76a..9b0a538 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -11,6 +11,7 @@
#include <asm/processor.h>
#include <asm/fsl_law.h>
#include <asm/errno.h>
+#include <asm/fsl_errata.h>
#include "fsl_corenet2_serdes.h"
#ifdef CONFIG_SYS_FSL_SRDS_1
@@ -203,108 +204,125 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask,
u32 sd_prctl_shift)
* This workaround for the protocols and rates that only have the Ring VCO.
*/
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
- sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
- debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
+ if (!not_has_erratum_a007186()) {
+ sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
+ debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
- sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
+ sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
- if (sel == 0x01 || sel == 0x02) {
- for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
- pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
- debug("A007186: pll_num=%x pllcr0=%x\n",
- pll_num, pll_status);
- /* STEP 1 */
- /* Read factory pre-set SerDes calibration values
- * from fuse block(SFP scratch register-sfp_spfr0)
- */
- switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
- case SRDS_PLLCR0_FRATE_SEL_3_0:
- case SRDS_PLLCR0_FRATE_SEL_3_072:
- debug("A007186: 3.0/3.072 protocol rate\n");
- bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
- dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
- fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
- break;
- case SRDS_PLLCR0_FRATE_SEL_3_125:
- debug("A007186: 3.125 protocol rate\n");
- bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
- dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
- fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
- break;
- case SRDS_PLLCR0_FRATE_SEL_3_75:
- debug("A007186: 3.75 protocol rate\n");
- bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
- dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
- fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
- break;
- default:
- continue;
- }
+ if (sel == 0x01 || sel == 0x02) {
+ for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
+ pll_status = in_be32(&srds_regs->
+ bank[pll_num].pllcr0);
+ debug("A007186: pll_num=%x pllcr0=%x\n",
+ pll_num, pll_status);
+ /* STEP 1 */
+ /* Read factory pre-set SerDes calibration
+ * values from fuse block(SFP scratch
+ * register-sfp_spfr0)
+ */
+ switch (pll_status &
+ SRDS_PLLCR0_FRATE_SEL_MASK) {
+ case SRDS_PLLCR0_FRATE_SEL_3_0:
+ case SRDS_PLLCR0_FRATE_SEL_3_072:
+ debug("A007186: ");
+ debug("3.0/3.072 protocol rate\n");
+ bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+ break;
+ case SRDS_PLLCR0_FRATE_SEL_3_125:
+ debug("A007186: 3.125 protocol rate\n");
+ bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
+ break;
+ case SRDS_PLLCR0_FRATE_SEL_3_75:
+ debug("A007186: 3.75 protocol rate\n");
+ bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+ break;
+ default:
+ continue;
+ }
- /* STEP 2 */
- /* Write SRDSxPLLnCR1[11:16] = FC
- * Write SRDSxPLLnCR1[2] = BC
- */
- pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
- pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
- ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
- out_be32(&srds_regs->bank[pll_num].pllcr1,
- (pll_cr_upd | pll_cr1));
- debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
- pll_num, (pll_cr_upd | pll_cr1));
- /* Write SRDSxPLLnCR0[24:26] = DC
- */
- pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
- out_be32(&srds_regs->bank[pll_num].pllcr0,
- pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
- debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
- pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
- /* Write SRDSxPLLnCR1[3] = 1
- * Write SRDSxPLLnCR1[6] = 1
- */
- pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
- pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
- out_be32(&srds_regs->bank[pll_num].pllcr1,
- (pll_cr_upd | pll_cr1));
- debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
- pll_num, (pll_cr_upd | pll_cr1));
+ /* STEP 2 */
+ /* Write SRDSxPLLnCR1[11:16] = FC
+ * Write SRDSxPLLnCR1[2] = BC
+ */
+ pll_cr1 = in_be32(&srds_regs->
+ bank[pll_num].pllcr1);
+ pll_cr_upd = (((bc << CR1_BCAP_SHIFT) &
+ BCAP_MASK) |
+ ((fc << CR1_FCAP_SHIFT) &
+ FCAP_MASK));
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ (pll_cr_upd | pll_cr1));
+ debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+ pll_num, (pll_cr_upd | pll_cr1));
+ /* Write SRDSxPLLnCR0[24:26] = DC
+ */
+ pll_cr0 = in_be32(&srds_regs->
+ bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0,
+ pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
+ debug("A007186: pll_num=%x, Update PLLCR0=%x\n",
+ pll_num,
+ (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
+ /* Write SRDSxPLLnCR1[3] = 1
+ * Write SRDSxPLLnCR1[6] = 1
+ */
+ pll_cr1 = in_be32(&srds_regs->
+ bank[pll_num].pllcr1);
+ pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ (pll_cr_upd | pll_cr1));
+ debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+ pll_num, (pll_cr_upd | pll_cr1));
- /* STEP 3 */
- /* Read the status Registers */
- /* Verify SRDSxPLLnSR2[8] = BC */
- pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
- debug("A007186: pll_num=%x pllsr2=%x\n",
- pll_num, pll_sr2);
- bc_status = (pll_sr2 >> 23) & BC_MASK;
- if (bc_status != bc)
- debug("BC mismatch\n");
- fc_status = (pll_sr2 >> 16) & FC_MASK;
- if (fc_status != fc)
- debug("FC mismatch\n");
- pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
- out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
- 0x02000000);
- pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
- dc_status = (pll_sr2 >> 17) & DC_MASK;
- if (dc_status != dc)
- debug("DC mismatch\n");
- pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
- out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
- 0xfdffffff);
+ /* STEP 3 */
+ /* Read the status Registers */
+ /* Verify SRDSxPLLnSR2[8] = BC */
+ pll_sr2 = in_be32(&srds_regs->
+ bank[pll_num].pllsr2);
+ debug("A007186: pll_num=%x pllsr2=%x\n",
+ pll_num, pll_sr2);
+ bc_status = (pll_sr2 >> 23) & BC_MASK;
+ if (bc_status != bc)
+ debug("BC mismatch\n");
+ fc_status = (pll_sr2 >> 16) & FC_MASK;
+ if (fc_status != fc)
+ debug("FC mismatch\n");
+ pll_cr0 = in_be32(&srds_regs->
+ bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0,
+ pll_cr0 | 0x02000000);
+ pll_sr2 = in_be32(&srds_regs->
+ bank[pll_num].pllsr2);
+ dc_status = (pll_sr2 >> 17) & DC_MASK;
+ if (dc_status != dc)
+ debug("DC mismatch\n");
+ pll_cr0 = in_be32(&srds_regs->
+ bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0,
+ pll_cr0 & 0xfdffffff);
- /* STEP 4 */
- /* Wait 750us to verify the PLL is locked
- * by checking SRDSxPLLnCR0[8] = 1.
- */
- udelay(750);
- pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
- debug("A007186: pll_num=%x pllcr0=%x\n",
- pll_num, pll_status);
+ /* STEP 4 */
+ /* Wait 750us to verify the PLL is locked
+ * by checking SRDSxPLLnCR0[8] = 1.
+ */
+ udelay(750);
+ pll_status = in_be32(&srds_regs->
+ bank[pll_num].pllcr0);
+ debug("A007186: pll_num=%x pllcr0=%x\n",
+ pll_num, pll_status);
- if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
- printf("A007186 Serdes PLL not locked\n");
- else
- debug("A007186 Serdes PLL locked\n");
+ if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
+ debug("A007186 Serdes PLL not lock\n");
+ else
+ debug("A007186 Serdes PLL lock\n");
+ }
}
}
#endif
diff --git a/arch/powerpc/include/asm/fsl_errata.h
b/arch/powerpc/include/asm/fsl_errata.h
index 64da4bb..a977544 100644
--- a/arch/powerpc/include/asm/fsl_errata.h
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -82,3 +82,17 @@ static inline bool has_erratum_a007075(void)
return false;
}
#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+static inline bool not_has_erratum_a007186(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ if (((soc == SVR_T2080) && (SVR_MAJ(svr) > 1)) ||
+ ((soc == SVR_T2080) && (SVR_MAJ(svr) == 1) && (SVR_MIN(svr) > 0)))
+ return true;
+
+ return false;
+}
+#endif
--
2.1.0.27.g96db324
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