On Fri, Mar 27, 2009 at 1:32 AM, Dave Liu <dave...@freescale.com> wrote:
> Currently the clk_adj is 6 (3/4 cycle), The settings will cause > the DDR controller hang at the data init. Change the clk_adj > from 6 to 4 (1/2 cycle), make the memory system stable. > > Signed-off-by: Dave Liu <dave...@freescale.com> Applied to HEAD, thanks! Andy
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