Hi Stefan,
see one comment below.
> The Marvell bridge 64360 supports serveral PCI functions, not only 0. This
> patch enables access to those functions.
>
> Signed-off-by: Stefan Roese <s...@denx.de>
> Cc: Reinhard Arlt <reinhard.a...@esd-electronics.com>
> ---
> board/esd/cpci750/cpci750.c | 16 +++++++++++-----
> board/esd/cpci750/pci.c | 14 +++++++++-----
> 2 files changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
> index 69ae517..18944ef 100644
> --- a/board/esd/cpci750/cpci750.c
> +++ b/board/esd/cpci750/cpci750.c
> @@ -187,6 +187,7 @@ original ppcboot 1.1.6 source end */
> static void gt_pci_config (void)
> {
> unsigned int stat;
> + unsigned int data;
> unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11,
> FuncNum 10:8, RegNum 7:2 */
>
> /* In PCIX mode devices provide their own bus and device numbers. We
> query the Discovery II's
> @@ -254,10 +255,11 @@ static void gt_pci_config (void)
>
> /*ronen update the pci internal registers base address.*/
> #ifdef MAP_PCI
> - for (stat = 0; stat <= PCI_HOST1; stat++)
> - pciWriteConfigReg (stat,
> -
> PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
> - SELF, CONFIG_SYS_GT_REGS);
> + for (stat = 0; stat <= PCI_HOST1; stat++) {
> + data = pciReadConfigReg(stat,
> PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, SELF);
> + data = (data & 0x0f) | CONFIG_SYS_GT_REGS;
> + pciWriteConfigReg (stat,
> PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, SELF, data);
Please break those long lines.
Matthias
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
