Hi,
On 07/11/14 10:55, Hyungwon Hwang wrote:
> This patch adds support for Odroid-XU3.
>
> Signed-off-by: Hyungwon Hwang <human.hw...@samsung.com>
> Cc: Minkyu Kang <mk7.k...@samsung.com>
> Cc: Lukasz Majewski <l.majew...@samsung.com>
> ---
> Changes for v3:
> - Remove unnecessary node from DT file
> - Remove unnecessary features from config file
> - Remove unnecessary macros from board-specific header file
> - Fix some trivial typos in comments
> Changes for v4:
> - Add MMC FIFO buffer's configuration to DT file
> - Make CONFIG_OF_CONTROL be set by the target information
> - Add basic document to doc/README.odroid-xu3
> - Add CONFIG_CMD_EXT4 to config file
> - Add environment size and offset to config file
> - Add extra default environment to make bootable without modification
> - Remove unnecessary features from config file
> Changes for v5:
> - Convert /include/ to #include in DT file
> arch/arm/cpu/armv7/exynos/Kconfig | 5 ++
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/exynos5422-odroidxu3.dts | 60 ++++++++++++++
> board/samsung/odroid-xu3/Kconfig | 12 +++
> board/samsung/odroid-xu3/MAINTAINERS | 6 ++
> board/samsung/odroid-xu3/Makefile | 7 ++
> board/samsung/odroid-xu3/odroid-xu3.c | 131 +++++++++++++++++++++++++++++++
> board/samsung/odroid-xu3/setup.h | 95 ++++++++++++++++++++++
> configs/odroid-xu3_defconfig | 4 +
> doc/README.odroid-xu3 | 134 +++++++++++++++++++++++++++++++
> include/configs/odroid_xu3.h | 144
> ++++++++++++++++++++++++++++++++++
> 11 files changed, 600 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts
> create mode 100644 board/samsung/odroid-xu3/Kconfig
> create mode 100644 board/samsung/odroid-xu3/MAINTAINERS
> create mode 100644 board/samsung/odroid-xu3/Makefile
> create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c
> create mode 100644 board/samsung/odroid-xu3/setup.h
> create mode 100644 configs/odroid-xu3_defconfig
> create mode 100644 doc/README.odroid-xu3
> create mode 100644 include/configs/odroid_xu3.h
>
> diff --git a/arch/arm/cpu/armv7/exynos/Kconfig
> b/arch/arm/cpu/armv7/exynos/Kconfig
> index 13dbd95..8fe530c 100644
> --- a/arch/arm/cpu/armv7/exynos/Kconfig
> +++ b/arch/arm/cpu/armv7/exynos/Kconfig
> @@ -24,6 +24,10 @@ config TARGET_TRATS2
> config TARGET_ODROID
> bool "Exynos4412 Odroid board"
>
> +config TARGET_ODROID_XU3
> + bool "Exynos5422 Odroid board"
> + select OF_CONTROL if !SPL_BUILD
> +
> config TARGET_ARNDALE
> bool "Exynos5250 Arndale board"
> select SUPPORT_SPL
> @@ -65,6 +69,7 @@ source "board/samsung/universal_c210/Kconfig"
> source "board/samsung/origen/Kconfig"
> source "board/samsung/trats2/Kconfig"
> source "board/samsung/odroid/Kconfig"
> +source "board/samsung/odroid-xu3/Kconfig"
> source "board/samsung/arndale/Kconfig"
> source "board/samsung/smdk5250/Kconfig"
> source "board/samsung/smdk5420/Kconfig"
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 2b9bd93..d984f34 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
> exynos5250-smdk5250.dtb \
> exynos5420-smdk5420.dtb \
> exynos5420-peach-pit.dtb \
> - exynos5800-peach-pi.dtb
> + exynos5800-peach-pi.dtb \
> + exynos5422-odroidxu3.dtb
> dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
> tegra20-medcom-wide.dtb \
> tegra20-paz00.dtb \
> diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts
> b/arch/arm/dts/exynos5422-odroidxu3.dts
> new file mode 100644
> index 0000000..52199d9
> --- /dev/null
> +++ b/arch/arm/dts/exynos5422-odroidxu3.dts
> @@ -0,0 +1,60 @@
> +/*
> + * Odroid XU3 device tree source
> + *
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +/dts-v1/;
> +#include "exynos54xx.dtsi"
> +
> +/ {
> + model = "Odroid XU3 based on EXYNOS5422";
> + compatible = "samsung,odroidxu3", "samsung,exynos5";
> +
> + aliases {
> + serial0 = "/serial@12C00000";
> + console = "/serial@12C20000";
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x40000000 0x10000000
> + 0x50000000 0x10000000
> + 0x60000000 0x10000000
> + 0x70000000 0x10000000
> + 0x80000000 0x10000000
> + 0x90000000 0x10000000
> + 0xa0000000 0x10000000
> + 0xb0000000 0xea00000>;
> + };
> +
> + serial@12C20000 {
> + status="okay";
> + };
> +
> + mmc@12200000 {
> + samsung,bus-width = <8>;
> + samsung,timing = <1 3 3>;
> + samsung,removable = <0>;
> + samsung,pre-init;
> + fifoth_val = <0x200f0020>;
> + };
> +
> + mmc@12210000 {
> + status = "disabled";
> + };
> +
> + mmc@12220000 {
> + samsung,bus-width = <4>;
> + samsung,timing = <1 2 3>;
> + samsung,removable = <1>;
> + fifoth_val = <0x200f0020>;
> + };
> +
> + mmc@12230000 {
> + status = "disabled";
> + };
> +};
> diff --git a/board/samsung/odroid-xu3/Kconfig
> b/board/samsung/odroid-xu3/Kconfig
> new file mode 100644
> index 0000000..6159692
> --- /dev/null
> +++ b/board/samsung/odroid-xu3/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_ODROID_XU3
> +
> +config SYS_BOARD
> + default "odroid-xu3"
> +
> +config SYS_VENDOR
> + default "samsung"
> +
> +config SYS_CONFIG_NAME
> + default "odroid_xu3"
> +
> +endif
> diff --git a/board/samsung/odroid-xu3/MAINTAINERS
> b/board/samsung/odroid-xu3/MAINTAINERS
> new file mode 100644
> index 0000000..50cf928
> --- /dev/null
> +++ b/board/samsung/odroid-xu3/MAINTAINERS
> @@ -0,0 +1,6 @@
> +ODROID-XU3 BOARD
> +M: Hyungwon Hwang <human.hw...@samsung.com>
> +S: Maintained
> +F: board/samsung/odroid-xu3/
> +F: include/configs/odroid_xu3.h
> +F: configs/odroid-xu3_defconfig
> diff --git a/board/samsung/odroid-xu3/Makefile
> b/board/samsung/odroid-xu3/Makefile
> new file mode 100644
> index 0000000..85ae5c5
> --- /dev/null
> +++ b/board/samsung/odroid-xu3/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y := odroid-xu3.o
> diff --git a/board/samsung/odroid-xu3/odroid-xu3.c
> b/board/samsung/odroid-xu3/odroid-xu3.c
> new file mode 100644
> index 0000000..ea39487
> --- /dev/null
> +++ b/board/samsung/odroid-xu3/odroid-xu3.c
> @@ -0,0 +1,131 @@
> +/*
> + * Copyright (C) 2014 Samsung Electronics
> + * Hyungwon Hwang <human.hw...@samsung.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <netdev.h>
is netdev needed?
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/power.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/mmc.h>
> +#include <asm/arch/pinmux.h>
> +#include <asm/arch/sromc.h>
> +#include "setup.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +unsigned int get_board_rev(void)
> +{
> + unsigned int rev = 0;
> + return rev;
I think it's a meaningless.
just return 0;
> +}
> +
> +int exynos_init(void)
> +{
> + return 0;
> +}
> +
> +static int board_clock_init(void)
This function will be dead if CONFIG_BOARD_EARLY_INIT_F is not defined.
> +{
> + unsigned int set, clr, clr_src_cpu, clr_pll_con0;
> + struct exynos5420_clock *clk = (struct exynos5420_clock *)
> + samsung_get_base_clock();
> + /*
> + * CMU_CPU clocks src to MPLL
> + * Bit values: 0 ; 1
> + * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
> + * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
> + * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
> + * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
> + */
> +
> + /* Set CMU_CPU clocks src to OSCCLK */
> + clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);
> + set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);
> +
> + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
> +
> + while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
> + continue;
> +
> + /* Set APLL to 1200MHz */
> + clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
> + PLL_ENABLE(1);
> + set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);
> +
> + clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
> +
> + while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
> + continue;
> +
> + /* Set CMU_CPU clocks src to APLL */
> + set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);
> + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
> +
> + while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
> + continue;
> +
> + clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |
> + PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);
> + set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |
> + PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);
> +
> + clrsetbits_le32(&clk->div_cpu0, clr, set);
> +
> + while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
> + continue;
> +
> + /* Set MPLL to 800MHz */
> + set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);
> +
> + clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
> +
> + while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
> + continue;
> +
> + /* Set CLKMUX_UART src to MPLL */
> + clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | UART3_SEL(7);
> + set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | UART3_SEL(3);
> +
> + clrsetbits_le32(&clk->src_peric0, clr, set);
> +
> + /* Set SCLK_UART to 400 MHz (MPLL / 2) */
> + clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
> + UART3_RATIO(15);
> + set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |
> + UART3_RATIO(1);
> +
> + clrsetbits_le32(&clk->div_peric0, clr, set);
> +
> + while (readl(&clk->div_stat_peric0) & DIV_STAT_PERIC0_CHANGING)
> + continue;
> +
> + /* Set CLKMUX_MMC src to MPLL */
> + clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);
> + set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);
> +
> + clrsetbits_le32(&clk->src_fsys, clr, set);
> +
> + clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | MMC2_RATIO(0x3ff);
> + set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);
> +
> + clrsetbits_le32(&clk->div_fsys1, clr, set);
> +
> + /* Wait for divider ready status */
> + while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
> + continue;
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_BOARD_EARLY_INIT_F
> +int exynos_early_init_f(void)
> +{
> + return board_clock_init();
> +}
> +#endif
Thanks,
Minkyu Kang.
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