Hi!
> From: Dinh Nguyen <dingu...@opensource.altera.com>
>
> Set the PHY skew settings for the ethernet phy on the SOCFPGA
> devkit.
Should the timing configuration be done in the config file...?
Marek disliked getting the values from the environment, and I'm not
sure if that is neccessary. It can be removed if needed.
Signed-off-by: Pavel Machek <pa...@denx.de>
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 507b9a3..06a31b0 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -112,17 +112,46 @@ static int ksz9021_phy_extwrite(struct phy_device
*phydev, int addr,
return ksz9021_phy_extended_write(phydev, regnum, val);
}
+
+
/* Micrel ksz9021 */
static int ksz9021_config(struct phy_device *phydev)
{
unsigned ctrl1000 = 0;
const unsigned master = CTRL1000_PREFER_MASTER |
- CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
+ CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
unsigned features = phydev->drv->features;
+ printf("ksz9021: configuring\n");
+
+ printf("Configuring PHY skew timing for %s\n",
+ phydev->drv->name);
+
+ /* min rx data delay */
+ if (ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+
getenv_ulong(CONFIG_KSZ9021_DATA_SKEW_ENV, 16,
+
CONFIG_KSZ9021_DATA_SKEW_VAL)) < 0)
+ return -1;
+ /* min tx data delay */
+ if (ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+
getenv_ulong(CONFIG_KSZ9021_DATA_SKEW_ENV, 16,
+
CONFIG_KSZ9021_DATA_SKEW_VAL)) < 0)
+ return -1;
+ /* max rx/tx clock delay, min rx/tx control */
+ if (ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+
getenv_ulong(CONFIG_KSZ9021_CLK_SKEW_ENV, 16,
+
CONFIG_KSZ9021_CLK_SKEW_VAL)) < 0)
+ return -1;
+
+
+
+
if (getenv("disable_giga"))
features &= ~(SUPPORTED_1000baseT_Half |
- SUPPORTED_1000baseT_Full);
+ SUPPORTED_1000baseT_Full);
/* force master mode for 1000BaseT due to chip errata */
if (features & SUPPORTED_1000baseT_Half)
ctrl1000 |= ADVERTISE_1000HALF | master;
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index 8d54bf89..53a3d71 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -53,19 +56,29 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
-#define CONFIG_EPHY0_PHY_ADDR 0
-
-/* PHY */
#define CONFIG_EPHY1_PHY_ADDR 4
+
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+/* phy */
+#define CONFIG_EPHY0_PHY_ADDR 0
+#define CONFIG_EPHY1_PHY_ADDR 4
+#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+/* Type of PHY available */
+#define SOCFPGA_PHYSEL_ENUM_GMII 0x0
+#define SOCFPGA_PHYSEL_ENUM_MII 0x1
+#define SOCFPGA_PHYSEL_ENUM_RGMII 0x2
+#define SOCFPGA_PHYSEL_ENUM_RMII 0x3
+
+
+#else
+#error Youll need ethernet :-)
#endif
/* Extra Environment */
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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