Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to use consistent name XXX_ADDR for binary blobs
Makefile | 2 +-
arch/x86/cpu/ivybridge/sdram.c | 2 +-
arch/x86/cpu/queensbay/Kconfig | 4 ++--
arch/x86/cpu/queensbay/fsp_support.c | 2 +-
arch/x86/cpu/queensbay/tnc_car.S | 2 +-
include/configs/chromebook_link.h | 2 +-
6 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/Makefile b/Makefile
index d4e60e8..41137a5 100644
--- a/Makefile
+++ b/Makefile
@@ -958,7 +958,7 @@ IFDTOOL_ME_FLAGS += -i
ME:$(srctree)/board/$(BOARDDIR)/me.bin
endif
ifneq ($(CONFIG_HAVE_MRC),)
-IFDTOOL_FLAGS += -w
$(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin
+IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
endif
ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index df2b990..b95e781 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -177,7 +177,7 @@ int sdram_initialise(struct pei_data *pei_data)
debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
- data = (char *)CONFIG_X86_MRC_START;
+ data = (char *)CONFIG_X86_MRC_ADDR;
if (data) {
int rv;
int (*func)(struct pei_data *);
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 56fe85c..f6b5201 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -29,7 +29,7 @@ config FSP_FILE
The filename of the file to use as Firmware Support Package binary
in the board directory.
-config FSP_LOCATION
+config FSP_ADDR
hex "Firmware Support Package binary location"
depends on HAVE_FSP
default 0xfffc0000
@@ -65,7 +65,7 @@ config CMC_FILE
The filename of the file to use as Chipset Micro Code state machine
binary in the board directory.
-config CMC_LOCATION
+config CMC_ADDR
hex "Chipset Micro Code state machine binary location"
depends on HAVE_CMC
default 0xfffb0000
diff --git a/arch/x86/cpu/queensbay/fsp_support.c
b/arch/x86/cpu/queensbay/fsp_support.c
index df3bbd0..f830eeb 100644
--- a/arch/x86/cpu/queensbay/fsp_support.c
+++ b/arch/x86/cpu/queensbay/fsp_support.c
@@ -64,7 +64,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void)
volatile register u8 *fsp asm("eax");
/* Initalize the FSP base */
- fsp = (u8 *)CONFIG_FSP_LOCATION;
+ fsp = (u8 *)CONFIG_FSP_ADDR;
/* Check the FV signature, _FVH */
if (((struct fv_header_t *)fsp)->sign == 0x4856465F) {
diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S
index 2e9139e..5e09568 100644
--- a/arch/x86/cpu/queensbay/tnc_car.S
+++ b/arch/x86/cpu/queensbay/tnc_car.S
@@ -29,7 +29,7 @@ find_fsp_header_ret:
mov %eax, %ebp
/* sanity test */
- cmp $CONFIG_FSP_LOCATION, %eax
+ cmp $CONFIG_FSP_ADDR, %eax
jb die
/* calculate TempRamInitEntry address */
diff --git a/include/configs/chromebook_link.h
b/include/configs/chromebook_link.h
index 645b31c..c9d84e4 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -25,7 +25,7 @@
#define CONFIG_X86_RESET_VECTOR
#define CONFIG_NR_DRAM_BANKS 8
-#define CONFIG_X86_MRC_START 0xfffa0000
+#define CONFIG_X86_MRC_ADDR 0xfffa0000
#define CONFIG_CACHE_MRC_SIZE_KB 512
#define CONFIG_COREBOOT_SERIAL
--
1.8.2.1
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