Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.
Signed-off-by: Simon Glass <s...@chromium.org>
---
arch/x86/dts/link.dts | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index 1ebc334..c322510 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -8,6 +8,10 @@
model = "Google Link";
compatible = "google,link", "intel,celeron-ivybridge";
+ aliases {
+ spi0 = "/spi";
+ };
+
config {
silent_console = <0>;
};
@@ -155,11 +159,20 @@
spi {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "intel,ich9";
+ compatible = "intel,ich9-spi";
spi-flash@0 {
+ #size-cells = <1>;
+ #address-cells = <1>;
reg = <0>;
compatible = "winbond,w25q64", "spi-flash";
memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ /* Alignment: 4k (for updating) */
+ reg = <0x003e0000 0x00010000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
};
};
--
2.2.0.rc0.207.ga3a616c
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
