On 2014-12-29 15:08, Ian Campbell wrote: > On Mon, 2014-12-15 at 12:37 +0100, Jan Kiszka wrote: >> + movw r8, #(GICC_BASE & 0xffff) >> + movt r8, #(GICC_BASE >> 16) >> + ldr r9, [r8, #GICC_IAR] >> + movw r10, #0x3ff >> + movt r10, #0 >> + cmp r9, r10 >> + beq out >> + movw r10, #0x3fe >> + cmp r9, r10 >> + beq out >> + str r9, [r8, #GICC_EOIR] >> + dsb > > This block could do with a leading comment like the others. It is > reading IAR and discarding any spurious interrupts (1022+1023), but not > explicitly checking for SGI15, presumably because it can be asserted > that there is no other possible interrupt which can end up here, is that > right?
That would be my interpretations as well: no other interrupt was routed to the monitor. Will add a comment. > >> + >> +.globl psci_cpu_off >> +psci_cpu_off: >> + mrc p15, 0, r0, c1, c0, 0 @ SCTLR >> + bic r0, r0, #(1 << 2) @ Clear C bit >> + mcr p15, 0, r0, c1, c0, 0 @ SCTLR >> + isb >> + dsb >> + >> + bl v7_flush_dcache_all >> + >> + clrex @ Why??? > > Anyone got any clues? (Just curiosity, not a blocker) > > Apart from the comment: > Acked-by: Ian Campbell <i...@hellion.org.uk> > Thanks, Jan
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