On 01/14/2015 09:12 AM, Vijay Rai wrote: > T1040RDB_D4 board is a variant of T1040RDB(DDR3) board with DDR4 memory. > > Similarily T1042RDB_D4 is a variant of T1042RDB(DDR3) board with DDR4 > memory. >
It is helpful to add what DDR4 DIMM has been tested here. > Changes related to Ethernet > - Add support for 0x66 serdes protocol for T1040RDB_D4 Board > - Add support for 0x86 serdes protocol for T1042RDB_D4 Board > > Signed-off-by: Vijay Rai <vijay....@freescale.com> > Signed-off-by: Priyanka Jain <priyanka.j...@freescale.com> > --- > board/freescale/t104xrdb/MAINTAINERS | 8 +++++ > board/freescale/t104xrdb/ddr.c | 8 +++++ > board/freescale/t104xrdb/ddr.h | 12 ++++++++ > board/freescale/t104xrdb/eth.c | 20 +++++++++++-- > board/freescale/t104xrdb/t1040_d4_rcw.cfg | 7 +++++ > board/freescale/t104xrdb/t1042_d4_rcw.cfg | 7 +++++ > configs/T1040RDB_D4_NAND_defconfig | 5 ++++ > configs/T1040RDB_D4_SDCARD_defconfig | 5 ++++ > configs/T1040RDB_D4_SPIFLASH_defconfig | 5 ++++ > configs/T1040RDB_D4_defconfig | 4 +++ > configs/T1042RDB_D4_NAND_defconfig | 5 ++++ > configs/T1042RDB_D4_SDCARD_defconfig | 5 ++++ > configs/T1042RDB_D4_SPIFLASH_defconfig | 5 ++++ > configs/T1042RDB_D4_defconfig | 4 +++ > include/configs/T104xRDB.h | 46 > +++++++++++++++++++++++------ > 15 files changed, 135 insertions(+), 11 deletions(-) > create mode 100644 board/freescale/t104xrdb/t1040_d4_rcw.cfg > create mode 100644 board/freescale/t104xrdb/t1042_d4_rcw.cfg > create mode 100644 configs/T1040RDB_D4_NAND_defconfig > create mode 100644 configs/T1040RDB_D4_SDCARD_defconfig > create mode 100644 configs/T1040RDB_D4_SPIFLASH_defconfig > create mode 100644 configs/T1040RDB_D4_defconfig > create mode 100644 configs/T1042RDB_D4_NAND_defconfig > create mode 100644 configs/T1042RDB_D4_SDCARD_defconfig > create mode 100644 configs/T1042RDB_D4_SPIFLASH_defconfig > create mode 100644 configs/T1042RDB_D4_defconfig > > diff --git a/board/freescale/t104xrdb/MAINTAINERS > b/board/freescale/t104xrdb/MAINTAINERS > index b61e1c0..fc3bebb 100644 > --- a/board/freescale/t104xrdb/MAINTAINERS > +++ b/board/freescale/t104xrdb/MAINTAINERS > @@ -6,7 +6,13 @@ F: include/configs/T104xRDB.h > F: configs/T1040RDB_defconfig > F: configs/T1040RDB_NAND_defconfig > F: configs/T1040RDB_SPIFLASH_defconfig > +F: configs/T1040RDB_D4_defconfig > +F: configs/T1040RDB_D4_NAND_defconfig > +F: configs/T1040RDB_D4_SPIFLASH_defconfig > F: configs/T1042RDB_defconfig > +F: configs/T1042RDB_D4_defconfig > +F: configs/T1042RDB_D4_NAND_defconfig > +F: configs/T1042RDB_D4_SPIFLASH_defconfig > F: configs/T1042RDB_PI_defconfig > F: configs/T1042RDB_PI_NAND_defconfig > F: configs/T1042RDB_PI_SPIFLASH_defconfig > @@ -15,6 +21,8 @@ T1040RDB_SDCARD BOARD > #M: - > S: Maintained > F: configs/T1040RDB_SDCARD_defconfig > +F: configs/T1040RDB_D4_SDCARD_defconfig > +F: configs/T1042RDB_D4_SDCARD_defconfig > F: configs/T1042RDB_PI_SDCARD_defconfig > > T1040RDB_SECURE_BOOT BOARD > diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c > index 5aa11b1..b5083fe 100644 > --- a/board/freescale/t104xrdb/ddr.c > +++ b/board/freescale/t104xrdb/ddr.c > @@ -16,6 +16,7 @@ > > DECLARE_GLOBAL_DATA_PTR; > > +#ifdef CONFIG_SYS_FSL_DDR3 Wrong macro. If you don't need this code, it should be gated by CONFIG_SYS_DDR_RAW_TIMING. This board actually uses DIMM, doesn't it? I encourage you to send a cleanup patch to remove raw timing parameter code from this board. It is better to use SPD. > int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, > unsigned int controller_number, > unsigned int dimm_number) > @@ -30,6 +31,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, > > return 0; > } > +#endif > > void fsl_ddr_board_options(memctl_options_t *popts, > dimm_params_t *pdimm, > @@ -106,8 +108,14 @@ found: > popts->zq_en = 1; > > /* DHC_EN =1, ODT = 75 Ohm */ > +#ifdef CONFIG_SYS_FSL_DDR4 > + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); > + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | > + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ > +#else > popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); > popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); > +#endif > } > > #if defined(CONFIG_DEEP_SLEEP) > diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h > index 09b30b9..15175aa 100644 > --- a/board/freescale/t104xrdb/ddr.h > +++ b/board/freescale/t104xrdb/ddr.h > @@ -6,6 +6,7 @@ > > #ifndef __DDR_H__ > #define __DDR_H__ > +#ifdef CONFIG_SYS_FSL_DDR3 > dimm_params_t ddr_raw_timing = { > .n_ranks = 2, > .rank_density = 2147483648u, > @@ -34,6 +35,7 @@ dimm_params_t ddr_raw_timing = { > .refresh_rate_ps = 7800000, > .tfaw_ps = 35000, > }; > +#endif Likewise, I suggest to drop raw timing support for this board. It is not needed since SPD is working. > > struct board_specific_parameters { > u32 n_ranks; > @@ -57,6 +59,13 @@ static const struct board_specific_parameters udimm0[] = { > * num| hi| rank| clk| wrlvl | wrlvl > * ranks| mhz| GB |adjst| start | ctl2 > */ > +#ifdef CONFIG_SYS_FSL_DDR4 > + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, > + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A}, > + {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09}, > + {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A}, > + {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C}, > +#elif defined(CONFIG_SYS_FSL_DDR3) > {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, > {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, > {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, > @@ -69,6 +78,9 @@ static const struct board_specific_parameters udimm0[] = { > {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, > {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, > {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, > +#else > +#error DDR type not defined > +#endif > {} > }; > > diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c > index c8b6c67..b1477eb 100644 > --- a/board/freescale/t104xrdb/eth.c > +++ b/board/freescale/t104xrdb/eth.c > @@ -36,9 +36,11 @@ int board_eth_init(bd_t *bis) > int idx = i - FM1_DTSEC1; > > switch (fm_info_get_enet_if(i)) { > -#ifdef CONFIG_T1040RDB > +#if defined(CONFIG_T1040RDB) || (CONFIG_T1040RDB_D4) I think it is wrong to use CONFIG_T1040RDB_D4 here. See other comments. > case PHY_INTERFACE_MODE_SGMII: > - /* T1040RDB only supports SGMII on DTSEC3 */ > + /* T1040RDB & T1040RDB_D4 only supports SGMII on > + * DTSEC3 > + */ > fm_info_set_phy_address(FM1_DTSEC3, > CONFIG_SYS_SGMII1_PHY_ADDR); > break; > @@ -53,6 +55,20 @@ int board_eth_init(bd_t *bis) > CONFIG_SYS_SGMII1_PHY_ADDR); > break; > #endif > +#ifdef CONFIG_T1042RDB_D4 Isn't it the same as T1042RDB? > + case PHY_INTERFACE_MODE_SGMII: > + /* T1042RDB_D4 supports SGMII on DTSEC1, DTSEC2 > + * & DTSEC3 > + */ > + if (FM1_DTSEC1 == i) > + phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR; > + if (FM1_DTSEC2 == i) > + phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR; > + if (FM1_DTSEC3 == i) > + phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR; > + fm_info_set_phy_address(i, phy_addr); > + break; > +#endif > case PHY_INTERFACE_MODE_RGMII: > if (FM1_DTSEC4 == i) > phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; > diff --git a/board/freescale/t104xrdb/t1040_d4_rcw.cfg > b/board/freescale/t104xrdb/t1040_d4_rcw.cfg > new file mode 100644 > index 0000000..3300c18 > --- /dev/null > +++ b/board/freescale/t104xrdb/t1040_d4_rcw.cfg > @@ -0,0 +1,7 @@ > +#PBL preamble and RCW header > +aa55aa55 010e0100 > +# serdes protocol 0x66 > +0c18000e 0e000000 00000000 00000000 > +66000002 80000002 e8106000 01000000 > +00000000 00000000 00000000 00032810 > +00000000 0342500f 00000000 00000000 > diff --git a/board/freescale/t104xrdb/t1042_d4_rcw.cfg > b/board/freescale/t104xrdb/t1042_d4_rcw.cfg > new file mode 100644 > index 0000000..db4d52f > --- /dev/null > +++ b/board/freescale/t104xrdb/t1042_d4_rcw.cfg > @@ -0,0 +1,7 @@ > +#PBL preamble and RCW header > +aa55aa55 010e0100 > +# serdes protocol 0x86 > +0c18000e 0e000000 00000000 00000000 > +86000002 80000002 ec027000 01000000 > +00000000 00000000 00000000 00032810 > +00000000 0342500f 00000000 00000000 > diff --git a/configs/T1040RDB_D4_NAND_defconfig > b/configs/T1040RDB_D4_NAND_defconfig > new file mode 100644 > index 0000000..f0fa12b > --- /dev/null > +++ b/configs/T1040RDB_D4_NAND_defconfig > @@ -0,0 +1,5 @@ > +CONFIG_SPL=y > +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB_D4,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XRDB_D4" Do not add T104XRDB_D4. Instead, add SYS_FSL_DDR4. > ++S:CONFIG_PPC=y > ++S:CONFIG_MPC85xx=y > ++S:CONFIG_TARGET_T104XRDB=y > diff --git a/configs/T1040RDB_D4_SDCARD_defconfig > b/configs/T1040RDB_D4_SDCARD_defconfig > new file mode 100644 > index 0000000..d0f8b06 > --- /dev/null > +++ b/configs/T1040RDB_D4_SDCARD_defconfig > @@ -0,0 +1,5 @@ > +CONFIG_SPL=y > +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB_D4,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XRDB_D4" Same here. > ++S:CONFIG_PPC=y > ++S:CONFIG_MPC85xx=y > ++S:CONFIG_TARGET_T104XRDB=y > diff --git a/configs/T1040RDB_D4_SPIFLASH_defconfig > b/configs/T1040RDB_D4_SPIFLASH_defconfig > new file mode 100644 > index 0000000..da48906 > --- /dev/null > +++ b/configs/T1040RDB_D4_SPIFLASH_defconfig > @@ -0,0 +1,5 @@ > +CONFIG_SPL=y > +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB_D4,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T10XxRDB_D4" Same here. > ++S:CONFIG_PPC=y > ++S:CONFIG_MPC85xx=y > ++S:CONFIG_TARGET_T104XRDB=y > diff --git a/configs/T1040RDB_D4_defconfig b/configs/T1040RDB_D4_defconfig > new file mode 100644 > index 0000000..c13afab > --- /dev/null > +++ b/configs/T1040RDB_D4_defconfig > @@ -0,0 +1,4 @@ > +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB_D4,T104XRDB_D4" Same here. > +CONFIG_PPC=y > +CONFIG_MPC85xx=y > +CONFIG_TARGET_T104XRDB=y > diff --git a/configs/T1042RDB_D4_NAND_defconfig > b/configs/T1042RDB_D4_NAND_defconfig > new file mode 100644 > index 0000000..d08dd72 > --- /dev/null > +++ b/configs/T1042RDB_D4_NAND_defconfig > @@ -0,0 +1,5 @@ > +CONFIG_SPL=y > +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_D4,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XRDB_D4" Same. > ++S:CONFIG_PPC=y > ++S:CONFIG_MPC85xx=y > ++S:CONFIG_TARGET_T104XRDB=y > diff --git a/configs/T1042RDB_D4_SDCARD_defconfig > b/configs/T1042RDB_D4_SDCARD_defconfig > new file mode 100644 > index 0000000..b913282 > --- /dev/null > +++ b/configs/T1042RDB_D4_SDCARD_defconfig > @@ -0,0 +1,5 @@ > +CONFIG_SPL=y > +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_D4,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XRDB_D4" Same. > ++S:CONFIG_PPC=y > ++S:CONFIG_MPC85xx=y > ++S:CONFIG_TARGET_T104XRDB=y > diff --git a/configs/T1042RDB_D4_SPIFLASH_defconfig > b/configs/T1042RDB_D4_SPIFLASH_defconfig > new file mode 100644 > index 0000000..d43bd78 > --- /dev/null > +++ b/configs/T1042RDB_D4_SPIFLASH_defconfig > @@ -0,0 +1,5 @@ > +CONFIG_SPL=y > +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_D4,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XRDB_D4" Same > ++S:CONFIG_PPC=y > ++S:CONFIG_MPC85xx=y > ++S:CONFIG_TARGET_T104XRDB=y > diff --git a/configs/T1042RDB_D4_defconfig b/configs/T1042RDB_D4_defconfig > new file mode 100644 > index 0000000..39c79c4 > --- /dev/null > +++ b/configs/T1042RDB_D4_defconfig > @@ -0,0 +1,4 @@ > +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_D4,T104XRDB_D4" Same. > +CONFIG_PPC=y > +CONFIG_MPC85xx=y > +CONFIG_TARGET_T104XRDB=y > diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h > index 57cdf72..dbfcfee 100644 > --- a/include/configs/T104xRDB.h > +++ b/include/configs/T104xRDB.h > @@ -29,6 +29,14 @@ > #ifdef CONFIG_T1042RDB > #define CONFIG_SYS_FSL_PBL_RCW > $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg > #endif > +#ifdef CONFIG_T1040RDB_D4 > +#define CONFIG_SYS_FSL_PBL_RCW \ > +$(SRCTREE)/board/freescale/t104xrdb/t1040_d4_rcw.cfg > +#endif > +#ifdef CONFIG_T1042RDB_D4 > +#define CONFIG_SYS_FSL_PBL_RCW \ > +$(SRCTREE)/board/freescale/t104xrdb/t1042_d4_rcw.cfg > +#endif > Use #if, #elif, #endif. > #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT > #define CONFIG_SPL_ENV_SUPPORT > @@ -219,9 +227,15 @@ > #define CONFIG_DIMM_SLOTS_PER_CTLR 1 > #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) > > +#ifdef CONFIG_T104XRDB_D4 Do not add this macro. > +#define CONFIG_SYS_FSL_DDR4 > +#endif > + > #define CONFIG_DDR_SPD > +#ifndef CONFIG_SYS_FSL_DDR4 > #define CONFIG_SYS_DDR_RAW_TIMING Drop RAW timing, preferred in a separated patch. > #define CONFIG_SYS_FSL_DDR3 > +#endif > > #define CONFIG_SYS_SPD_BUS_NUM 0 > #define SPD_EEPROM_ADDRESS 0x51 > @@ -279,7 +293,7 @@ > #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ > #define CPLD_LBMAP_RESET 0xFF > #define CPLD_LBMAP_SHIFT 0x03 > -#ifdef CONFIG_T1042RDB_PI > +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XRDB_D4) What? Is it similar to _PI board? I am going to stop here. > #define CPLD_DIU_SEL_DFP 0x80 > #endif > > @@ -449,7 +463,7 @@ > #define CONFIG_SYS_HUSH_PARSER > #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > > -#ifdef CONFIG_T1042RDB_PI > +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XRDB_D4) > /* Video */ > #define CONFIG_FSL_DIU_FB > > @@ -494,11 +508,11 @@ > > /* I2C bus multiplexer */ > #define I2C_MUX_PCA_ADDR 0x70 > -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) > +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XRDB_D4) > #define I2C_MUX_CH_DEFAULT 0x8 > #endif > > -#ifdef CONFIG_T1042RDB_PI > +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XRDB_D4) > /* LDI/DVI Encoder for display */ > #define CONFIG_SYS_I2C_LDI_ADDR 0x38 > #define CONFIG_SYS_I2C_DVI_ADDR 0x75 > @@ -667,7 +681,7 @@ > #define CONFIG_SYS_DPAA_FMAN > #define CONFIG_SYS_DPAA_PME > > -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) > +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XDB_D4) > #define CONFIG_QE > #define CONFIG_U_QE > #endif > @@ -696,7 +710,7 @@ > #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 > #endif > > -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) > +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XRDB_D4) > #if defined(CONFIG_SPIFLASH) > #define CONFIG_SYS_QE_FW_ADDR 0x130000 > #elif defined(CONFIG_SDCARD) > @@ -721,10 +735,20 @@ > > #ifdef CONFIG_FMAN_ENET > #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) > -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 > +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 > +#elif defined(CONFIG_T1040RDB_D4) || defined(CONFIG_T1042RDB_D4) > +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 > +#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 > +#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 > +#endif > + > +#ifdef CONFIG_T104XRDB_D4 > +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 > +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 > +#else > +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 > +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 > #endif > -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 > -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 > > #define CONFIG_MII /* MII PHY management */ > #define CONFIG_ETHPRIME "FM1@DTSEC4" > @@ -835,6 +859,10 @@ > #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" > #elif defined(CONFIG_T1042RDB) > #define FDTFILE "t1042rdb/t1042rdb.dtb" > +#elif defined(CONFIG_T1040RDB_D4) > +#define FDTFILE "t1042rdb/t1040rdb_d4.dtb" > +#elif defined(CONFIG_T1042RDB_D4) > +#define FDTFILE "t1042rdb/t1042rdb_d4.dtb" > #endif > Why using different device tree? It should be the same RDB device tree with only memory size fixup, right? > #ifdef CONFIG_FSL_DIU_FB > Please respin this patch. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot